[LV] Fix PR45525: Incorrect assert in blend recipe

Fix an assert introduced in 41ed5d856c1: a phi with a single predecessor and a
mask is a valid case which is already supported by the code.

Differential Revision: https://reviews.llvm.org/D78115
This commit is contained in:
Gil Rapaport 2020-04-14 17:20:41 +03:00
parent 2cd0be02b9
commit b747d72c19
3 changed files with 47 additions and 7 deletions

View File

@ -7463,8 +7463,11 @@ void VPBlendRecipe::execute(VPTransformState &State) {
// Generate a sequence of selects of the form:
// SELECT(Mask3, In3,
// SELECT(Mask2, In2,
// ( ...)))
// SELECT(Mask2, In2,
// SELECT(Mask1, In1,
// In0)))
// Note that Mask0 is never used: lanes for which no path reaches this phi and
// are essentially undef are taken from In0.
InnerLoopVectorizer::VectorParts Entry(State.UF);
for (unsigned In = 0; In < NumIncoming; ++In) {
for (unsigned Part = 0; Part < State.UF; ++Part) {

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@ -929,16 +929,16 @@ class VPBlendRecipe : public VPRecipeBase {
/// The blend operation is a User of the incoming values and of their
/// respective masks, ordered [I0, M0, I1, M1, ...]. Note that a single value
/// would be incoming with a full mask for which there is no VPValue.
/// might be incoming with a full mask for which there is no VPValue.
VPUser User;
public:
VPBlendRecipe(PHINode *Phi, ArrayRef<VPValue *> Operands)
: VPRecipeBase(VPBlendSC), Phi(Phi), User(Operands) {
assert(((Operands.size() == 1) ||
(Operands.size() > 2 && Operands.size() % 2 == 0)) &&
"Expected either a single incoming value or a greater than two and "
"even number of operands");
assert(Operands.size() > 0 &&
((Operands.size() == 1) || (Operands.size() % 2 == 0)) &&
"Expected either a single incoming value or a positive even number "
"of operands");
}
/// Method to support type inquiry through isa, cast, and dyn_cast.

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@ -0,0 +1,37 @@
; RUN: opt < %s -loop-vectorize -force-vector-width=4 -S | FileCheck %s
; Test case for PR45525. Checks that phi's with a single predecessor and a mask are supported.
define void @main(i1 %cond, i32* %arr) {
; CHECK-LABEL: @main(
; CHECK-NEXT: bb.0:
; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
; CHECK: vector.ph:
; CHECK: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
; CHECK: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
; CHECK: [[TMP5:%.*]] = mul <4 x i32> [[VEC_IND]], <i32 3, i32 3, i32 3, i32 3>
;
bb.0:
br label %bb.1
bb.1: ; preds = %bb.3, %bb.0
%iv = phi i32 [ 0, %bb.0 ], [ %iv.next, %bb.3 ]
br i1 %cond, label %bb.3, label %bb.2
bb.2: ; preds = %bb.1
%single.pred = phi i32 [ %iv, %bb.1 ]
%mult = mul i32 %single.pred, 3
br label %bb.3
bb.3: ; preds = %bb.2, %bb.1
%stored.value = phi i32 [ 7, %bb.1 ], [ %mult, %bb.2 ]
%arrayidx = getelementptr inbounds i32, i32* %arr, i32 %iv
store i32 %stored.value, i32* %arrayidx
%iv.next = add i32 %iv, 1
%continue = icmp ult i32 %iv.next, 32
br i1 %continue, label %bb.1, label %bb.4
bb.4: ; preds = %bb.3
ret void
}