forked from OSchip/llvm-project
[AArch64][GlobalISel] Select FCMPSri/FCMPDri when comparing against 0.0
Add support for selecting FCMPSri and FCMPDri when comparing against 0.0, and factor out opcode selection for G_FCMP into its own function. Add a test to show that we don't do this with other immediates. Differential Revision: https://reviews.llvm.org/D62539 llvm-svn: 361888
This commit is contained in:
Jessica Paquette
parent
1efbe67414
commit
b73ea75b38
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@ -741,6 +741,20 @@ static unsigned selectFPConvOpc(unsigned GenericOpc, LLT DstTy, LLT SrcTy) {
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return GenericOpc;
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}
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/// Helper function to select the opcode for a G_FCMP.
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static unsigned selectFCMPOpc(MachineInstr &I, MachineRegisterInfo &MRI) {
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// If this is a compare against +0.0, then we don't have to explicitly
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// materialize a constant.
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const ConstantFP *FPImm = getConstantFPVRegVal(I.getOperand(3).getReg(), MRI);
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bool ShouldUseImm = FPImm && (FPImm->isZero() && !FPImm->isNegative());
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unsigned OpSize = MRI.getType(I.getOperand(2).getReg()).getSizeInBits();
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if (OpSize != 32 && OpSize != 64)
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return 0;
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unsigned CmpOpcTbl[2][2] = {{AArch64::FCMPSrr, AArch64::FCMPDrr},
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{AArch64::FCMPSri, AArch64::FCMPDri}};
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return CmpOpcTbl[ShouldUseImm][OpSize == 64];
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}
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static AArch64CC::CondCode changeICMPPredToAArch64CC(CmpInst::Predicate P) {
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switch (P) {
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default:
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@ -1845,15 +1859,9 @@ bool AArch64InstructionSelector::select(MachineInstr &I,
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return false;
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}
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unsigned CmpOpc = 0;
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LLT CmpTy = MRI.getType(I.getOperand(2).getReg());
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if (CmpTy == LLT::scalar(32)) {
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CmpOpc = AArch64::FCMPSrr;
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} else if (CmpTy == LLT::scalar(64)) {
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CmpOpc = AArch64::FCMPDrr;
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} else {
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unsigned CmpOpc = selectFCMPOpc(I, MRI);
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if (!CmpOpc)
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return false;
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}
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// FIXME: regbank
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@ -1861,9 +1869,16 @@ bool AArch64InstructionSelector::select(MachineInstr &I,
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changeFCMPPredToAArch64CC(
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(CmpInst::Predicate)I.getOperand(1).getPredicate(), CC1, CC2);
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MachineInstr &CmpMI = *BuildMI(MBB, I, I.getDebugLoc(), TII.get(CmpOpc))
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.addUse(I.getOperand(2).getReg())
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.addUse(I.getOperand(3).getReg());
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// Partially build the compare. Decide if we need to add a use for the
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// third operand based off whether or not we're comparing against 0.0.
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auto CmpMI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(CmpOpc))
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.addUse(I.getOperand(2).getReg());
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// If we don't have an immediate compare, then we need to add a use of the
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// register which wasn't used for the immediate.
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// Note that the immediate will always be the last operand.
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if (CmpOpc != AArch64::FCMPSri && CmpOpc != AArch64::FCMPDri)
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CmpMI = CmpMI.addUse(I.getOperand(3).getReg());
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const unsigned DefReg = I.getOperand(0).getReg();
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unsigned Def1Reg = DefReg;
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@ -1893,8 +1908,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I,
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constrainSelectedInstRegOperands(OrMI, TII, TRI, RBI);
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constrainSelectedInstRegOperands(CSet2MI, TII, TRI, RBI);
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}
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constrainSelectedInstRegOperands(CmpMI, TII, TRI, RBI);
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constrainSelectedInstRegOperands(*CmpMI, TII, TRI, RBI);
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constrainSelectedInstRegOperands(CSetMI, TII, TRI, RBI);
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I.eraseFromParent();
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@ -0,0 +1,56 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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# Verify that we get FCMPSri when we compare against 0.0 and that we get
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# FCMPSrr otherwise.
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...
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---
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name: zero
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $s0, $s1
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; CHECK-LABEL: name: zero
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; CHECK: liveins: $s0, $s1
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; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK: FCMPSri [[COPY]], implicit-def $nzcv
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; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK: $s0 = COPY [[CSINCWr]]
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; CHECK: RET_ReallyLR implicit $s0
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%0:fpr(s32) = COPY $s0
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%1:fpr(s32) = COPY $s1
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%2:fpr(s32) = G_FCONSTANT float 0.000000e+00
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%3:gpr(s32) = G_FCMP floatpred(oeq), %0(s32), %2
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$s0 = COPY %3(s32)
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RET_ReallyLR implicit $s0
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...
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---
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name: notzero
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.1:
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liveins: $s0, $s1
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; CHECK-LABEL: name: notzero
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; CHECK: liveins: $s0, $s1
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; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK: [[FMOVSi:%[0-9]+]]:fpr32 = FMOVSi 112
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; CHECK: FCMPSrr [[COPY]], [[FMOVSi]], implicit-def $nzcv
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; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK: $s0 = COPY [[CSINCWr]]
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; CHECK: RET_ReallyLR implicit $s0
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%0:fpr(s32) = COPY $s0
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%1:fpr(s32) = COPY $s1
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%2:fpr(s32) = G_FCONSTANT float 1.000000e+00
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%3:gpr(s32) = G_FCMP floatpred(oeq), %0(s32), %2
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$s0 = COPY %3(s32)
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RET_ReallyLR implicit $s0
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