forked from OSchip/llvm-project
[AArch64] Regenerate some test checks. NFC
This regenerates some of the tests that had very-close-to-updated check line already, in order to make them more maintainable.
This commit is contained in:
David Green
parent
c24fc37e47
commit
b737f1acf4
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@ -1,35 +1,44 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=arm64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
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declare <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8>, <8 x i8>)
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declare <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8>, <8 x i8>)
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define <8 x i8> @test_uabd_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
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; CHECK: test_uabd_v8i8:
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; CHECK-LABEL: test_uabd_v8i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uabd v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: ret
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%abd = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
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; CHECK: uabd v0.8b, v0.8b, v1.8b
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ret <8 x i8> %abd
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}
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define <8 x i8> @test_uaba_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
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; CHECK: test_uaba_v8i8:
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; CHECK-LABEL: test_uaba_v8i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uaba v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: ret
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%abd = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
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%aba = add <8 x i8> %lhs, %abd
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; CHECK: uaba v0.8b, v0.8b, v1.8b
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ret <8 x i8> %aba
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}
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define <8 x i8> @test_sabd_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
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; CHECK: test_sabd_v8i8:
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; CHECK-LABEL: test_sabd_v8i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sabd v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: ret
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%abd = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
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; CHECK: sabd v0.8b, v0.8b, v1.8b
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ret <8 x i8> %abd
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}
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define <8 x i8> @test_saba_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
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; CHECK: test_saba_v8i8:
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; CHECK-LABEL: test_saba_v8i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: saba v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: ret
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%abd = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
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%aba = add <8 x i8> %lhs, %abd
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; CHECK: saba v0.8b, v0.8b, v1.8b
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ret <8 x i8> %aba
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}
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@ -37,32 +46,40 @@ declare <16 x i8> @llvm.aarch64.neon.uabd.v16i8(<16 x i8>, <16 x i8>)
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declare <16 x i8> @llvm.aarch64.neon.sabd.v16i8(<16 x i8>, <16 x i8>)
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define <16 x i8> @test_uabd_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
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; CHECK: test_uabd_v16i8:
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; CHECK-LABEL: test_uabd_v16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uabd v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%abd = call <16 x i8> @llvm.aarch64.neon.uabd.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
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; CHECK: uabd v0.16b, v0.16b, v1.16b
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ret <16 x i8> %abd
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}
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define <16 x i8> @test_uaba_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
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; CHECK: test_uaba_v16i8:
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; CHECK-LABEL: test_uaba_v16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uaba v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%abd = call <16 x i8> @llvm.aarch64.neon.uabd.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
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%aba = add <16 x i8> %lhs, %abd
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; CHECK: uaba v0.16b, v0.16b, v1.16b
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ret <16 x i8> %aba
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}
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define <16 x i8> @test_sabd_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
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; CHECK: test_sabd_v16i8:
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; CHECK-LABEL: test_sabd_v16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sabd v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%abd = call <16 x i8> @llvm.aarch64.neon.sabd.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
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; CHECK: sabd v0.16b, v0.16b, v1.16b
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ret <16 x i8> %abd
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}
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define <16 x i8> @test_saba_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
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; CHECK: test_saba_v16i8:
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; CHECK-LABEL: test_saba_v16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: saba v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%abd = call <16 x i8> @llvm.aarch64.neon.sabd.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
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%aba = add <16 x i8> %lhs, %abd
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; CHECK: saba v0.16b, v0.16b, v1.16b
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ret <16 x i8> %aba
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}
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@ -70,32 +87,40 @@ declare <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16>, <4 x i16>)
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declare <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16>, <4 x i16>)
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define <4 x i16> @test_uabd_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
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; CHECK: test_uabd_v4i16:
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; CHECK-LABEL: test_uabd_v4i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uabd v0.4h, v0.4h, v1.4h
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; CHECK-NEXT: ret
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%abd = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
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; CHECK: uabd v0.4h, v0.4h, v1.4h
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ret <4 x i16> %abd
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}
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define <4 x i16> @test_uaba_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
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; CHECK: test_uaba_v4i16:
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; CHECK-LABEL: test_uaba_v4i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uaba v0.4h, v0.4h, v1.4h
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; CHECK-NEXT: ret
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%abd = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
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%aba = add <4 x i16> %lhs, %abd
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; CHECK: uaba v0.4h, v0.4h, v1.4h
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ret <4 x i16> %aba
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}
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define <4 x i16> @test_sabd_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
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; CHECK: test_sabd_v4i16:
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; CHECK-LABEL: test_sabd_v4i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sabd v0.4h, v0.4h, v1.4h
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; CHECK-NEXT: ret
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%abd = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
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; CHECK: sabd v0.4h, v0.4h, v1.4h
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ret <4 x i16> %abd
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}
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define <4 x i16> @test_saba_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
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; CHECK: test_saba_v4i16:
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; CHECK-LABEL: test_saba_v4i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: saba v0.4h, v0.4h, v1.4h
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; CHECK-NEXT: ret
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%abd = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
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%aba = add <4 x i16> %lhs, %abd
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; CHECK: saba v0.4h, v0.4h, v1.4h
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ret <4 x i16> %aba
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}
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@ -103,32 +128,40 @@ declare <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16>, <8 x i16>)
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declare <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16>, <8 x i16>)
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define <8 x i16> @test_uabd_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
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; CHECK: test_uabd_v8i16:
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; CHECK-LABEL: test_uabd_v8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uabd v0.8h, v0.8h, v1.8h
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; CHECK-NEXT: ret
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%abd = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
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; CHECK: uabd v0.8h, v0.8h, v1.8h
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ret <8 x i16> %abd
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}
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define <8 x i16> @test_uaba_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
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; CHECK: test_uaba_v8i16:
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; CHECK-LABEL: test_uaba_v8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uaba v0.8h, v0.8h, v1.8h
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; CHECK-NEXT: ret
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%abd = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
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%aba = add <8 x i16> %lhs, %abd
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; CHECK: uaba v0.8h, v0.8h, v1.8h
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ret <8 x i16> %aba
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}
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define <8 x i16> @test_sabd_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
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; CHECK: test_sabd_v8i16:
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; CHECK-LABEL: test_sabd_v8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sabd v0.8h, v0.8h, v1.8h
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; CHECK-NEXT: ret
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%abd = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
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; CHECK: sabd v0.8h, v0.8h, v1.8h
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ret <8 x i16> %abd
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}
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define <8 x i16> @test_saba_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
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; CHECK: test_saba_v8i16:
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; CHECK-LABEL: test_saba_v8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: saba v0.8h, v0.8h, v1.8h
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; CHECK-NEXT: ret
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%abd = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
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%aba = add <8 x i16> %lhs, %abd
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; CHECK: saba v0.8h, v0.8h, v1.8h
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ret <8 x i16> %aba
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}
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@ -136,31 +169,41 @@ declare <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32>, <2 x i32>)
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declare <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32>, <2 x i32>)
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define <2 x i32> @test_uabd_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
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; CHECK: test_uabd_v2i32:
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; CHECK-LABEL: test_uabd_v2i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uabd v0.2s, v0.2s, v1.2s
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; CHECK-NEXT: ret
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%abd = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
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; CHECK: uabd v0.2s, v0.2s, v1.2s
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ret <2 x i32> %abd
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}
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define <2 x i32> @test_uaba_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
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; CHECK: test_uaba_v2i32:
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; CHECK-LABEL: test_uaba_v2i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uaba v0.2s, v0.2s, v1.2s
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; CHECK-NEXT: ret
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%abd = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
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%aba = add <2 x i32> %lhs, %abd
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; CHECK: uaba v0.2s, v0.2s, v1.2s
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ret <2 x i32> %aba
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}
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define <2 x i32> @test_sabd_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
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; CHECK: test_sabd_v2i32:
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; CHECK-LABEL: test_sabd_v2i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sabd v0.2s, v0.2s, v1.2s
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; CHECK-NEXT: ret
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%abd = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
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; CHECK: sabd v0.2s, v0.2s, v1.2s
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ret <2 x i32> %abd
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}
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define <2 x i32> @test_sabd_v2i32_const() {
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; CHECK: test_sabd_v2i32_const:
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; CHECK: movi d1, #0x00ffffffff0000
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; CHECK-NEXT: sabd v0.2s, v0.2s, v1.2s
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; CHECK-LABEL: test_sabd_v2i32_const:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI19_0
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; CHECK-NEXT: ldr d0, [x8, :lo12:.LCPI19_0]
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; CHECK-NEXT: movi d1, #0x00ffffffff0000
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; CHECK-NEXT: sabd v0.2s, v0.2s, v1.2s
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; CHECK-NEXT: ret
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%1 = tail call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(
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<2 x i32> <i32 -2147483648, i32 2147450880>,
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<2 x i32> <i32 -65536, i32 65535>)
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@ -168,10 +211,12 @@ define <2 x i32> @test_sabd_v2i32_const() {
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}
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define <2 x i32> @test_saba_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
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; CHECK: test_saba_v2i32:
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; CHECK-LABEL: test_saba_v2i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: saba v0.2s, v0.2s, v1.2s
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; CHECK-NEXT: ret
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%abd = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
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%aba = add <2 x i32> %lhs, %abd
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; CHECK: saba v0.2s, v0.2s, v1.2s
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ret <2 x i32> %aba
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}
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@ -179,58 +224,72 @@ declare <4 x i32> @llvm.aarch64.neon.uabd.v4i32(<4 x i32>, <4 x i32>)
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declare <4 x i32> @llvm.aarch64.neon.sabd.v4i32(<4 x i32>, <4 x i32>)
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define <4 x i32> @test_uabd_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
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; CHECK: test_uabd_v4i32:
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; CHECK-LABEL: test_uabd_v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uabd v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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%abd = call <4 x i32> @llvm.aarch64.neon.uabd.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
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; CHECK: uabd v0.4s, v0.4s, v1.4s
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ret <4 x i32> %abd
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}
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define <4 x i32> @test_uaba_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
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; CHECK: test_uaba_v4i32:
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; CHECK-LABEL: test_uaba_v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uaba v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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%abd = call <4 x i32> @llvm.aarch64.neon.uabd.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
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%aba = add <4 x i32> %lhs, %abd
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; CHECK: uaba v0.4s, v0.4s, v1.4s
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ret <4 x i32> %aba
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}
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define <4 x i32> @test_sabd_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
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; CHECK: test_sabd_v4i32:
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; CHECK-LABEL: test_sabd_v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sabd v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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%abd = call <4 x i32> @llvm.aarch64.neon.sabd.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
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; CHECK: sabd v0.4s, v0.4s, v1.4s
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ret <4 x i32> %abd
|
||||
}
|
||||
|
||||
define <4 x i32> @test_saba_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
|
||||
; CHECK: test_saba_v4i32:
|
||||
; CHECK-LABEL: test_saba_v4i32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: saba v0.4s, v0.4s, v1.4s
|
||||
; CHECK-NEXT: ret
|
||||
%abd = call <4 x i32> @llvm.aarch64.neon.sabd.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
|
||||
%aba = add <4 x i32> %lhs, %abd
|
||||
; CHECK: saba v0.4s, v0.4s, v1.4s
|
||||
ret <4 x i32> %aba
|
||||
}
|
||||
|
||||
declare <2 x float> @llvm.aarch64.neon.fabd.v2f32(<2 x float>, <2 x float>)
|
||||
|
||||
define <2 x float> @test_fabd_v2f32(<2 x float> %lhs, <2 x float> %rhs) {
|
||||
; CHECK: test_fabd_v2f32:
|
||||
; CHECK-LABEL: test_fabd_v2f32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fabd v0.2s, v0.2s, v1.2s
|
||||
; CHECK-NEXT: ret
|
||||
%abd = call <2 x float> @llvm.aarch64.neon.fabd.v2f32(<2 x float> %lhs, <2 x float> %rhs)
|
||||
; CHECK: fabd v0.2s, v0.2s, v1.2s
|
||||
ret <2 x float> %abd
|
||||
}
|
||||
|
||||
declare <4 x float> @llvm.aarch64.neon.fabd.v4f32(<4 x float>, <4 x float>)
|
||||
|
||||
define <4 x float> @test_fabd_v4f32(<4 x float> %lhs, <4 x float> %rhs) {
|
||||
; CHECK: test_fabd_v4f32:
|
||||
; CHECK-LABEL: test_fabd_v4f32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fabd v0.4s, v0.4s, v1.4s
|
||||
; CHECK-NEXT: ret
|
||||
%abd = call <4 x float> @llvm.aarch64.neon.fabd.v4f32(<4 x float> %lhs, <4 x float> %rhs)
|
||||
; CHECK: fabd v0.4s, v0.4s, v1.4s
|
||||
ret <4 x float> %abd
|
||||
}
|
||||
|
||||
declare <2 x double> @llvm.aarch64.neon.fabd.v2f64(<2 x double>, <2 x double>)
|
||||
|
||||
define <2 x double> @test_fabd_v2f64(<2 x double> %lhs, <2 x double> %rhs) {
|
||||
; CHECK: test_fabd_v2f64:
|
||||
; CHECK-LABEL: test_fabd_v2f64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fabd v0.2d, v0.2d, v1.2d
|
||||
; CHECK-NEXT: ret
|
||||
%abd = call <2 x double> @llvm.aarch64.neon.fabd.v2f64(<2 x double> %lhs, <2 x double> %rhs)
|
||||
; CHECK: fabd v0.2d, v0.2d, v1.2d
|
||||
ret <2 x double> %abd
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,4 +1,5 @@
|
|||
; RUN: llc < %s -mtriple=arm64-apple-ios | FileCheck %s
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -mtriple=arm64-apple-ios -aarch64-enable-collect-loh=false | FileCheck %s
|
||||
|
||||
define void @test(float * %p1, i32 %v1) {
|
||||
; CHECK-LABEL: test:
|
||||
|
|
@ -50,9 +51,13 @@ entry:
|
|||
@_gv = external unnamed_addr global %"st1", align 8
|
||||
|
||||
define internal void @nvcast_f32_v8i8() {
|
||||
; CHECK-LABEL: _nvcast_f32_v8i8
|
||||
; CHECK: movi.8b v[[REG:[0-9]+]], #254
|
||||
; CHECK: str d[[REG]]
|
||||
; CHECK-LABEL: nvcast_f32_v8i8:
|
||||
; CHECK: ; %bb.0: ; %entry
|
||||
; CHECK-NEXT: adrp x8, __gv@GOTPAGE
|
||||
; CHECK-NEXT: ldr x8, [x8, __gv@GOTPAGEOFF]
|
||||
; CHECK-NEXT: movi.8b v0, #254
|
||||
; CHECK-NEXT: str d0, [x8]
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
store <2 x float> <float 0xC7DFDFDFC0000000, float 0xC7DFDFDFC0000000>, <2 x float>* bitcast (%"st1"* @_gv to <2 x float>*), align 8
|
||||
ret void
|
||||
|
|
@ -61,9 +66,11 @@ entry:
|
|||
%struct.Vector3 = type { float, float, float }
|
||||
|
||||
define void @nvcast_v2f32_v1f64(%struct.Vector3*) {
|
||||
; CHECK-LABEL: _nvcast_v2f32_v1f64
|
||||
; CHECK: fmov.2s v[[REG:[0-9]+]], #1.00000000
|
||||
; CHECK: str d[[REG]], [x0]
|
||||
; CHECK-LABEL: nvcast_v2f32_v1f64:
|
||||
; CHECK: ; %bb.0: ; %entry
|
||||
; CHECK-NEXT: fmov.2s v0, #1.00000000
|
||||
; CHECK-NEXT: str d0, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
%a13 = bitcast %struct.Vector3* %0 to <1 x double>*
|
||||
store <1 x double> <double 0x3F8000003F800000>, <1 x double>* %a13, align 8
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=arm64-apple-ios < %s | FileCheck %s
|
||||
; RUN: llc -mtriple=aarch64-linux-gnu < %s | FileCheck -check-prefix CHECK-NOTMACHO %s
|
||||
;
|
||||
|
|
@ -5,76 +6,94 @@
|
|||
|
||||
define void @odd() nounwind {
|
||||
; CHECK-LABEL: odd:
|
||||
; CHECK: stp d15, d14, [sp, #-144]!
|
||||
; CHECK: stp d13, d12, [sp, #16]
|
||||
; CHECK: stp d11, d10, [sp, #32]
|
||||
; CHECK: stp d9, d8, [sp, #48]
|
||||
; CHECK: stp x28, x27, [sp, #64]
|
||||
; CHECK: stp x26, x25, [sp, #80]
|
||||
; CHECK: stp x24, x23, [sp, #96]
|
||||
; CHECK: stp x22, x21, [sp, #112]
|
||||
; CHECK: stp x20, x19, [sp, #128]
|
||||
; CHECK: mov x0, #42
|
||||
; CHECK: ldp x20, x19, [sp, #128]
|
||||
; CHECK: ldp x22, x21, [sp, #112]
|
||||
; CHECK: ldp x24, x23, [sp, #96]
|
||||
; CHECK: ldp x26, x25, [sp, #80]
|
||||
; CHECK: ldp x28, x27, [sp, #64]
|
||||
; CHECK: ldp d9, d8, [sp, #48]
|
||||
; CHECK: ldp d11, d10, [sp, #32]
|
||||
; CHECK: ldp d13, d12, [sp, #16]
|
||||
; CHECK: ldp d15, d14, [sp], #144
|
||||
|
||||
; CHECK: ; %bb.0:
|
||||
; CHECK-NEXT: stp d15, d14, [sp, #-144]! ; 16-byte Folded Spill
|
||||
; CHECK-NEXT: stp d13, d12, [sp, #16] ; 16-byte Folded Spill
|
||||
; CHECK-NEXT: stp d11, d10, [sp, #32] ; 16-byte Folded Spill
|
||||
; CHECK-NEXT: stp d9, d8, [sp, #48] ; 16-byte Folded Spill
|
||||
; CHECK-NEXT: stp x28, x27, [sp, #64] ; 16-byte Folded Spill
|
||||
; CHECK-NEXT: stp x26, x25, [sp, #80] ; 16-byte Folded Spill
|
||||
; CHECK-NEXT: stp x24, x23, [sp, #96] ; 16-byte Folded Spill
|
||||
; CHECK-NEXT: stp x22, x21, [sp, #112] ; 16-byte Folded Spill
|
||||
; CHECK-NEXT: stp x20, x19, [sp, #128] ; 16-byte Folded Spill
|
||||
; CHECK-NEXT: ; InlineAsm Start
|
||||
; CHECK-NEXT: mov x0, #42
|
||||
; CHECK-NEXT: ; InlineAsm End
|
||||
; CHECK-NEXT: ldp x20, x19, [sp, #128] ; 16-byte Folded Reload
|
||||
; CHECK-NEXT: ldp x22, x21, [sp, #112] ; 16-byte Folded Reload
|
||||
; CHECK-NEXT: ldp x24, x23, [sp, #96] ; 16-byte Folded Reload
|
||||
; CHECK-NEXT: ldp x26, x25, [sp, #80] ; 16-byte Folded Reload
|
||||
; CHECK-NEXT: ldp x28, x27, [sp, #64] ; 16-byte Folded Reload
|
||||
; CHECK-NEXT: ldp d9, d8, [sp, #48] ; 16-byte Folded Reload
|
||||
; CHECK-NEXT: ldp d11, d10, [sp, #32] ; 16-byte Folded Reload
|
||||
; CHECK-NEXT: ldp d13, d12, [sp, #16] ; 16-byte Folded Reload
|
||||
; CHECK-NEXT: ldp d15, d14, [sp], #144 ; 16-byte Folded Reload
|
||||
; CHECK-NEXT: ret
|
||||
;
|
||||
; CHECK-NOTMACHO-LABEL: odd:
|
||||
; CHECK-NOTMACHO: stp d14, d12, [sp, #-80]!
|
||||
; CHECK-NOTMACHO: stp d10, d8, [sp, #16]
|
||||
; CHECK-NOTMACHO: str x27, [sp, #32]
|
||||
; CHECK-NOTMACHO: stp x25, x23, [sp, #48]
|
||||
; CHECK-NOTMACHO: stp x21, x19, [sp, #64]
|
||||
; CHECK-NOTMACHO: mov x0, #42
|
||||
; CHECK-NOTMACHO: ldp x21, x19, [sp, #64]
|
||||
; CHECK-NOTMACHO: ldp x25, x23, [sp, #48]
|
||||
; CHECK-NOTMACHO: ldr x27, [sp, #32]
|
||||
; CHECK-NOTMACHO: ldp d10, d8, [sp, #16]
|
||||
; CHECK-NOTMACHO: ldp d14, d12, [sp], #80
|
||||
; CHECK-NOTMACHO: // %bb.0:
|
||||
; CHECK-NOTMACHO-NEXT: stp d14, d12, [sp, #-80]! // 16-byte Folded Spill
|
||||
; CHECK-NOTMACHO-NEXT: stp d10, d8, [sp, #16] // 16-byte Folded Spill
|
||||
; CHECK-NOTMACHO-NEXT: str x27, [sp, #32] // 8-byte Folded Spill
|
||||
; CHECK-NOTMACHO-NEXT: stp x25, x23, [sp, #48] // 16-byte Folded Spill
|
||||
; CHECK-NOTMACHO-NEXT: stp x21, x19, [sp, #64] // 16-byte Folded Spill
|
||||
; CHECK-NOTMACHO-NEXT: //APP
|
||||
; CHECK-NOTMACHO-NEXT: mov x0, #42
|
||||
; CHECK-NOTMACHO-NEXT: //NO_APP
|
||||
; CHECK-NOTMACHO-NEXT: ldp x21, x19, [sp, #64] // 16-byte Folded Reload
|
||||
; CHECK-NOTMACHO-NEXT: ldp x25, x23, [sp, #48] // 16-byte Folded Reload
|
||||
; CHECK-NOTMACHO-NEXT: ldr x27, [sp, #32] // 8-byte Folded Reload
|
||||
; CHECK-NOTMACHO-NEXT: ldp d10, d8, [sp, #16] // 16-byte Folded Reload
|
||||
; CHECK-NOTMACHO-NEXT: ldp d14, d12, [sp], #80 // 16-byte Folded Reload
|
||||
; CHECK-NOTMACHO-NEXT: ret
|
||||
|
||||
call void asm sideeffect "mov x0, #42", "~{x0},~{x19},~{x21},~{x23},~{x25},~{x27},~{d8},~{d10},~{d12},~{d14}"() nounwind
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @even() nounwind {
|
||||
; CHECK-LABEL: even:
|
||||
; CHECK: stp d15, d14, [sp, #-144]!
|
||||
; CHECK: stp d13, d12, [sp, #16]
|
||||
; CHECK: stp d11, d10, [sp, #32]
|
||||
; CHECK: stp d9, d8, [sp, #48]
|
||||
; CHECK: stp x28, x27, [sp, #64]
|
||||
; CHECK: stp x26, x25, [sp, #80]
|
||||
; CHECK: stp x24, x23, [sp, #96]
|
||||
; CHECK: stp x22, x21, [sp, #112]
|
||||
; CHECK: stp x20, x19, [sp, #128]
|
||||
; CHECK: mov x0, #42
|
||||
; CHECK: ldp x20, x19, [sp, #128]
|
||||
; CHECK: ldp x22, x21, [sp, #112]
|
||||
; CHECK: ldp x24, x23, [sp, #96]
|
||||
; CHECK: ldp x26, x25, [sp, #80]
|
||||
; CHECK: ldp x28, x27, [sp, #64]
|
||||
; CHECK: ldp d9, d8, [sp, #48]
|
||||
; CHECK: ldp d11, d10, [sp, #32]
|
||||
; CHECK: ldp d13, d12, [sp, #16]
|
||||
; CHECK: ldp d15, d14, [sp], #144
|
||||
|
||||
; CHECK: ; %bb.0:
|
||||
; CHECK-NEXT: stp d15, d14, [sp, #-144]! ; 16-byte Folded Spill
|
||||
; CHECK-NEXT: stp d13, d12, [sp, #16] ; 16-byte Folded Spill
|
||||
; CHECK-NEXT: stp d11, d10, [sp, #32] ; 16-byte Folded Spill
|
||||
; CHECK-NEXT: stp d9, d8, [sp, #48] ; 16-byte Folded Spill
|
||||
; CHECK-NEXT: stp x28, x27, [sp, #64] ; 16-byte Folded Spill
|
||||
; CHECK-NEXT: stp x26, x25, [sp, #80] ; 16-byte Folded Spill
|
||||
; CHECK-NEXT: stp x24, x23, [sp, #96] ; 16-byte Folded Spill
|
||||
; CHECK-NEXT: stp x22, x21, [sp, #112] ; 16-byte Folded Spill
|
||||
; CHECK-NEXT: stp x20, x19, [sp, #128] ; 16-byte Folded Spill
|
||||
; CHECK-NEXT: ; InlineAsm Start
|
||||
; CHECK-NEXT: mov x0, #42
|
||||
; CHECK-NEXT: ; InlineAsm End
|
||||
; CHECK-NEXT: ldp x20, x19, [sp, #128] ; 16-byte Folded Reload
|
||||
; CHECK-NEXT: ldp x22, x21, [sp, #112] ; 16-byte Folded Reload
|
||||
; CHECK-NEXT: ldp x24, x23, [sp, #96] ; 16-byte Folded Reload
|
||||
; CHECK-NEXT: ldp x26, x25, [sp, #80] ; 16-byte Folded Reload
|
||||
; CHECK-NEXT: ldp x28, x27, [sp, #64] ; 16-byte Folded Reload
|
||||
; CHECK-NEXT: ldp d9, d8, [sp, #48] ; 16-byte Folded Reload
|
||||
; CHECK-NEXT: ldp d11, d10, [sp, #32] ; 16-byte Folded Reload
|
||||
; CHECK-NEXT: ldp d13, d12, [sp, #16] ; 16-byte Folded Reload
|
||||
; CHECK-NEXT: ldp d15, d14, [sp], #144 ; 16-byte Folded Reload
|
||||
; CHECK-NEXT: ret
|
||||
;
|
||||
; CHECK-NOTMACHO-LABEL: even:
|
||||
; CHECK-NOTMACHO: stp d15, d13, [sp, #-80]!
|
||||
; CHECK-NOTMACHO: stp d11, d9, [sp, #16]
|
||||
; CHECK-NOTMACHO: str x28, [sp, #32]
|
||||
; CHECK-NOTMACHO: stp x26, x24, [sp, #48]
|
||||
; CHECK-NOTMACHO: stp x22, x20, [sp, #64]
|
||||
; CHECK-NOTMACHO: mov x0, #42
|
||||
; CHECK-NOTMACHO: ldp x22, x20, [sp, #64]
|
||||
; CHECK-NOTMACHO: ldp x26, x24, [sp, #48]
|
||||
; CHECK-NOTMACHO: ldr x28, [sp, #32]
|
||||
; CHECK-NOTMACHO: ldp d11, d9, [sp, #16]
|
||||
; CHECK-NOTMACHO: ldp d15, d13, [sp], #80
|
||||
; CHECK-NOTMACHO: // %bb.0:
|
||||
; CHECK-NOTMACHO-NEXT: stp d15, d13, [sp, #-80]! // 16-byte Folded Spill
|
||||
; CHECK-NOTMACHO-NEXT: stp d11, d9, [sp, #16] // 16-byte Folded Spill
|
||||
; CHECK-NOTMACHO-NEXT: str x28, [sp, #32] // 8-byte Folded Spill
|
||||
; CHECK-NOTMACHO-NEXT: stp x26, x24, [sp, #48] // 16-byte Folded Spill
|
||||
; CHECK-NOTMACHO-NEXT: stp x22, x20, [sp, #64] // 16-byte Folded Spill
|
||||
; CHECK-NOTMACHO-NEXT: //APP
|
||||
; CHECK-NOTMACHO-NEXT: mov x0, #42
|
||||
; CHECK-NOTMACHO-NEXT: //NO_APP
|
||||
; CHECK-NOTMACHO-NEXT: ldp x22, x20, [sp, #64] // 16-byte Folded Reload
|
||||
; CHECK-NOTMACHO-NEXT: ldp x26, x24, [sp, #48] // 16-byte Folded Reload
|
||||
; CHECK-NOTMACHO-NEXT: ldr x28, [sp, #32] // 8-byte Folded Reload
|
||||
; CHECK-NOTMACHO-NEXT: ldp d11, d9, [sp, #16] // 16-byte Folded Reload
|
||||
; CHECK-NOTMACHO-NEXT: ldp d15, d13, [sp], #80 // 16-byte Folded Reload
|
||||
; CHECK-NOTMACHO-NEXT: ret
|
||||
|
||||
call void asm sideeffect "mov x0, #42", "~{x0},~{x20},~{x22},~{x24},~{x26},~{x28},~{d9},~{d11},~{d13},~{d15}"() nounwind
|
||||
ret void
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,11 +1,13 @@
|
|||
; RUN: llc < %s -asm-verbose=false -mtriple=arm64-apple-ios | FileCheck %s
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -mtriple=arm64-apple-ios | FileCheck %s
|
||||
|
||||
define <4 x float> @foo(<4 x float> %val, <4 x float> %test) nounwind {
|
||||
; CHECK-LABEL: foo:
|
||||
; CHECK-NEXT: fcmeq.4s v0, v0, v1
|
||||
; CHECK-NEXT: fmov.4s v1, #1.00000000
|
||||
; CHECK-NEXT: and.16b v0, v0, v1
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: ; %bb.0:
|
||||
; CHECK-NEXT: fcmeq.4s v0, v0, v1
|
||||
; CHECK-NEXT: fmov.4s v1, #1.00000000
|
||||
; CHECK-NEXT: and.16b v0, v0, v1
|
||||
; CHECK-NEXT: ret
|
||||
%cmp = fcmp oeq <4 x float> %val, %test
|
||||
%ext = zext <4 x i1> %cmp to <4 x i32>
|
||||
%result = sitofp <4 x i32> %ext to <4 x float>
|
||||
|
|
@ -16,9 +18,16 @@ define <4 x float> @foo(<4 x float> %val, <4 x float> %test) nounwind {
|
|||
; the folded nodes.
|
||||
define void @foo1(<4 x float> %val, <4 x float> %test, <4 x double>* %p) nounwind {
|
||||
; CHECK-LABEL: foo1:
|
||||
; CHECK: movi.4s
|
||||
; CHECK: scvtf.2d
|
||||
; CHECK: scvtf.2d
|
||||
; CHECK: ; %bb.0:
|
||||
; CHECK-NEXT: fcmeq.4s v0, v0, v1
|
||||
; CHECK-NEXT: movi.4s v1, #1
|
||||
; CHECK-NEXT: and.16b v0, v0, v1
|
||||
; CHECK-NEXT: ushll.2d v1, v0, #0
|
||||
; CHECK-NEXT: ushll2.2d v0, v0, #0
|
||||
; CHECK-NEXT: scvtf.2d v1, v1
|
||||
; CHECK-NEXT: scvtf.2d v0, v0
|
||||
; CHECK-NEXT: stp q1, q0, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%cmp = fcmp oeq <4 x float> %val, %test
|
||||
%ext = zext <4 x i1> %cmp to <4 x i32>
|
||||
%result = sitofp <4 x i32> %ext to <4 x double>
|
||||
|
|
@ -29,16 +38,16 @@ define void @foo1(<4 x float> %val, <4 x float> %test, <4 x double>* %p) nounwin
|
|||
; Fold explicit AND operations when the constant isn't a splat of a single
|
||||
; scalar value like what the zext creates.
|
||||
define <4 x float> @foo2(<4 x float> %val, <4 x float> %test) nounwind {
|
||||
; CHECK-LABEL: lCPI2_0:
|
||||
; CHECK-NEXT: .long 1065353216
|
||||
; CHECK-NEXT: .long 0
|
||||
; CHECK-NEXT: .long 1065353216
|
||||
; CHECK-NEXT: .long 0
|
||||
; CHECK-LABEL: foo2:
|
||||
; CHECK: adrp x8, lCPI2_0@PAGE
|
||||
; CHECK: ldr q2, [x8, lCPI2_0@PAGEOFF]
|
||||
; CHECK-NEXT: fcmeq.4s v0, v0, v1
|
||||
; CHECK-NEXT: and.16b v0, v0, v2
|
||||
; CHECK: ; %bb.0:
|
||||
; CHECK-NEXT: Lloh0:
|
||||
; CHECK-NEXT: adrp x8, lCPI2_0@PAGE
|
||||
; CHECK-NEXT: Lloh1:
|
||||
; CHECK-NEXT: ldr q2, [x8, lCPI2_0@PAGEOFF]
|
||||
; CHECK-NEXT: fcmeq.4s v0, v0, v1
|
||||
; CHECK-NEXT: and.16b v0, v0, v2
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK-NEXT: .loh AdrpLdr Lloh0, Lloh1
|
||||
%cmp = fcmp oeq <4 x float> %val, %test
|
||||
%ext = zext <4 x i1> %cmp to <4 x i32>
|
||||
%and = and <4 x i32> %ext, <i32 255, i32 256, i32 257, i32 258>
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
|
||||
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* 2>&1 | FileCheck %s --check-prefixes=CHECK,FALLBACK
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s --check-prefixes=CHECK,CHECKDAG
|
||||
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* 2>&1 | FileCheck %s --check-prefixes=CHECK,FALLBACK
|
||||
|
||||
; Test efficient codegen of vector extends up from legal type to 128 bit
|
||||
; and 256 bit vector types.
|
||||
|
|
@ -11,8 +12,9 @@
|
|||
; FALLBACK-NOT: remark:{{.*}}(in function: func1)
|
||||
define <8 x i16> @func1(<8 x i8> %v0) nounwind {
|
||||
; CHECK-LABEL: func1:
|
||||
; CHECK-NEXT: ushll.8h v0, v0, #0
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ushll.8h v0, v0, #0
|
||||
; CHECK-NEXT: ret
|
||||
%r = zext <8 x i8> %v0 to <8 x i16>
|
||||
ret <8 x i16> %r
|
||||
}
|
||||
|
|
@ -20,26 +22,29 @@ define <8 x i16> @func1(<8 x i8> %v0) nounwind {
|
|||
; FALLBACK-NOT: remark:{{.*}}(in function: func2)
|
||||
define <8 x i16> @func2(<8 x i8> %v0) nounwind {
|
||||
; CHECK-LABEL: func2:
|
||||
; CHECK-NEXT: sshll.8h v0, v0, #0
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: sshll.8h v0, v0, #0
|
||||
; CHECK-NEXT: ret
|
||||
%r = sext <8 x i8> %v0 to <8 x i16>
|
||||
ret <8 x i16> %r
|
||||
}
|
||||
|
||||
define <16 x i16> @func3(<16 x i8> %v0) nounwind {
|
||||
; CHECK-LABEL: func3:
|
||||
; CHECK-NEXT: ushll2.8h v1, v0, #0
|
||||
; CHECK-NEXT: ushll.8h v0, v0, #0
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ushll2.8h v1, v0, #0
|
||||
; CHECK-NEXT: ushll.8h v0, v0, #0
|
||||
; CHECK-NEXT: ret
|
||||
%r = zext <16 x i8> %v0 to <16 x i16>
|
||||
ret <16 x i16> %r
|
||||
}
|
||||
|
||||
define <16 x i16> @func4(<16 x i8> %v0) nounwind {
|
||||
; CHECK-LABEL: func4:
|
||||
; CHECK-NEXT: sshll2.8h v1, v0, #0
|
||||
; CHECK-NEXT: sshll.8h v0, v0, #0
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: sshll2.8h v1, v0, #0
|
||||
; CHECK-NEXT: sshll.8h v0, v0, #0
|
||||
; CHECK-NEXT: ret
|
||||
%r = sext <16 x i8> %v0 to <16 x i16>
|
||||
ret <16 x i16> %r
|
||||
}
|
||||
|
|
@ -51,8 +56,9 @@ define <16 x i16> @func4(<16 x i8> %v0) nounwind {
|
|||
; FALLBACK-NOT: remark:{{.*}}(in function: afunc1)
|
||||
define <4 x i32> @afunc1(<4 x i16> %v0) nounwind {
|
||||
; CHECK-LABEL: afunc1:
|
||||
; CHECK-NEXT: ushll.4s v0, v0, #0
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ushll.4s v0, v0, #0
|
||||
; CHECK-NEXT: ret
|
||||
%r = zext <4 x i16> %v0 to <4 x i32>
|
||||
ret <4 x i32> %r
|
||||
}
|
||||
|
|
@ -60,46 +66,51 @@ define <4 x i32> @afunc1(<4 x i16> %v0) nounwind {
|
|||
; FALLBACK-NOT: remark:{{.*}}(in function: afunc2)
|
||||
define <4 x i32> @afunc2(<4 x i16> %v0) nounwind {
|
||||
; CHECK-LABEL: afunc2:
|
||||
; CHECK-NEXT: sshll.4s v0, v0, #0
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: sshll.4s v0, v0, #0
|
||||
; CHECK-NEXT: ret
|
||||
%r = sext <4 x i16> %v0 to <4 x i32>
|
||||
ret <4 x i32> %r
|
||||
}
|
||||
|
||||
define <8 x i32> @afunc3(<8 x i16> %v0) nounwind {
|
||||
; CHECK-LABEL: afunc3:
|
||||
; CHECK-NEXT: ushll2.4s v1, v0, #0
|
||||
; CHECK-NEXT: ushll.4s v0, v0, #0
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ushll2.4s v1, v0, #0
|
||||
; CHECK-NEXT: ushll.4s v0, v0, #0
|
||||
; CHECK-NEXT: ret
|
||||
%r = zext <8 x i16> %v0 to <8 x i32>
|
||||
ret <8 x i32> %r
|
||||
}
|
||||
|
||||
define <8 x i32> @afunc4(<8 x i16> %v0) nounwind {
|
||||
; CHECK-LABEL: afunc4:
|
||||
; CHECK-NEXT: sshll2.4s v1, v0, #0
|
||||
; CHECK-NEXT: sshll.4s v0, v0, #0
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: sshll2.4s v1, v0, #0
|
||||
; CHECK-NEXT: sshll.4s v0, v0, #0
|
||||
; CHECK-NEXT: ret
|
||||
%r = sext <8 x i16> %v0 to <8 x i32>
|
||||
ret <8 x i32> %r
|
||||
}
|
||||
|
||||
define <8 x i32> @bfunc1(<8 x i8> %v0) nounwind {
|
||||
; CHECK-LABEL: bfunc1:
|
||||
; CHECK-NEXT: ushll.8h v0, v0, #0
|
||||
; CHECK-NEXT: ushll2.4s v1, v0, #0
|
||||
; CHECK-NEXT: ushll.4s v0, v0, #0
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ushll.8h v0, v0, #0
|
||||
; CHECK-NEXT: ushll2.4s v1, v0, #0
|
||||
; CHECK-NEXT: ushll.4s v0, v0, #0
|
||||
; CHECK-NEXT: ret
|
||||
%r = zext <8 x i8> %v0 to <8 x i32>
|
||||
ret <8 x i32> %r
|
||||
}
|
||||
|
||||
define <8 x i32> @bfunc2(<8 x i8> %v0) nounwind {
|
||||
; CHECK-LABEL: bfunc2:
|
||||
; CHECK-NEXT: sshll.8h v0, v0, #0
|
||||
; CHECK-NEXT: sshll2.4s v1, v0, #0
|
||||
; CHECK-NEXT: sshll.4s v0, v0, #0
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: sshll.8h v0, v0, #0
|
||||
; CHECK-NEXT: sshll2.4s v1, v0, #0
|
||||
; CHECK-NEXT: sshll.4s v0, v0, #0
|
||||
; CHECK-NEXT: ret
|
||||
%r = sext <8 x i8> %v0 to <8 x i32>
|
||||
ret <8 x i32> %r
|
||||
}
|
||||
|
|
@ -110,95 +121,99 @@ define <8 x i32> @bfunc2(<8 x i8> %v0) nounwind {
|
|||
|
||||
define <4 x i64> @zfunc1(<4 x i32> %v0) nounwind {
|
||||
; CHECK-LABEL: zfunc1:
|
||||
; CHECK-NEXT: ushll2.2d v1, v0, #0
|
||||
; CHECK-NEXT: ushll.2d v0, v0, #0
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ushll2.2d v1, v0, #0
|
||||
; CHECK-NEXT: ushll.2d v0, v0, #0
|
||||
; CHECK-NEXT: ret
|
||||
%r = zext <4 x i32> %v0 to <4 x i64>
|
||||
ret <4 x i64> %r
|
||||
}
|
||||
|
||||
define <4 x i64> @zfunc2(<4 x i32> %v0) nounwind {
|
||||
; CHECK-LABEL: zfunc2:
|
||||
; CHECK-NEXT: sshll2.2d v1, v0, #0
|
||||
; CHECK-NEXT: sshll.2d v0, v0, #0
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: sshll2.2d v1, v0, #0
|
||||
; CHECK-NEXT: sshll.2d v0, v0, #0
|
||||
; CHECK-NEXT: ret
|
||||
%r = sext <4 x i32> %v0 to <4 x i64>
|
||||
ret <4 x i64> %r
|
||||
}
|
||||
|
||||
define <4 x i64> @bfunc3(<4 x i16> %v0) nounwind {
|
||||
; CHECK-LABEL: func3:
|
||||
; CHECK-NEXT: ushll.4s v0, v0, #0
|
||||
; CHECK-NEXT: ushll2.2d v1, v0, #0
|
||||
; CHECK-NEXT: ushll.2d v0, v0, #0
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK-LABEL: bfunc3:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ushll.4s v0, v0, #0
|
||||
; CHECK-NEXT: ushll2.2d v1, v0, #0
|
||||
; CHECK-NEXT: ushll.2d v0, v0, #0
|
||||
; CHECK-NEXT: ret
|
||||
%r = zext <4 x i16> %v0 to <4 x i64>
|
||||
ret <4 x i64> %r
|
||||
}
|
||||
|
||||
define <4 x i64> @cfunc4(<4 x i16> %v0) nounwind {
|
||||
; CHECK-LABEL: func4:
|
||||
; CHECK-NEXT: sshll.4s v0, v0, #0
|
||||
; CHECK-NEXT: sshll2.2d v1, v0, #0
|
||||
; CHECK-NEXT: sshll.2d v0, v0, #0
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK-LABEL: cfunc4:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: sshll.4s v0, v0, #0
|
||||
; CHECK-NEXT: sshll2.2d v1, v0, #0
|
||||
; CHECK-NEXT: sshll.2d v0, v0, #0
|
||||
; CHECK-NEXT: ret
|
||||
%r = sext <4 x i16> %v0 to <4 x i64>
|
||||
ret <4 x i64> %r
|
||||
}
|
||||
|
||||
define <4 x i64> @zext_v4i8_to_v4i64(<4 x i8> %v0) nounwind {
|
||||
; CHECK-LABEL: zext_v4i8_to_v4i64:
|
||||
; CHECK-NEXT: bic.4h v0, #255, lsl #8
|
||||
; CHECK-NEXT: ushll.4s v0, v0, #0
|
||||
; CHECK-NEXT: ushll2.2d v1, v0, #0
|
||||
; CHECK-NEXT: ushll.2d v0, v0, #0
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: bic.4h v0, #255, lsl #8
|
||||
; CHECK-NEXT: ushll.4s v0, v0, #0
|
||||
; CHECK-NEXT: ushll2.2d v1, v0, #0
|
||||
; CHECK-NEXT: ushll.2d v0, v0, #0
|
||||
; CHECK-NEXT: ret
|
||||
;
|
||||
%r = zext <4 x i8> %v0 to <4 x i64>
|
||||
ret <4 x i64> %r
|
||||
}
|
||||
|
||||
define <4 x i64> @sext_v4i8_to_v4i64(<4 x i8> %v0) nounwind {
|
||||
; CHECK-LABEL: sext_v4i8_to_v4i64:
|
||||
; CHECK-NEXT: ushll.4s v0, v0, #0
|
||||
; CHECK-NEXT: ushll.2d v1, v0, #0
|
||||
; CHECK-NEXT: ushll2.2d v0, v0, #0
|
||||
; CHECK-NEXT: shl.2d v0, v0, #56
|
||||
; CHECK-NEXT: shl.2d v2, v1, #56
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ushll.4s v0, v0, #0
|
||||
; CHECK-NEXT: ushll.2d v1, v0, #0
|
||||
; CHECK-NEXT: ushll2.2d v0, v0, #0
|
||||
; CHECK-NEXT: shl.2d v0, v0, #56
|
||||
; CHECK-NEXT: shl.2d v2, v1, #56
|
||||
; CHECK-NEXT: sshr.2d v1, v0, #56
|
||||
; CHECK-NEXT: sshr.2d v0, v2, #56
|
||||
; CHECK-NEXT: ret
|
||||
;
|
||||
%r = sext <4 x i8> %v0 to <4 x i64>
|
||||
ret <4 x i64> %r
|
||||
}
|
||||
|
||||
define <8 x i64> @zext_v8i8_to_v8i64(<8 x i8> %v0) nounwind {
|
||||
; CHECK-LABEL: zext_v8i8_to_v8i64:
|
||||
; CHECK-NEXT: ushll.8h v0, v0, #0
|
||||
; CHECK-NEXT: ushll2.4s v2, v0, #0
|
||||
; CHECK-NEXT: ushll.4s v0, v0, #0
|
||||
; CHECK-NEXT: ushll2.2d v3, v2, #0
|
||||
; CHECK-NEXT: ushll2.2d v1, v0, #0
|
||||
; CHECK-NEXT: ushll.2d v2, v2, #0
|
||||
; CHECK-NEXT: ushll.2d v0, v0, #0
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ushll.8h v0, v0, #0
|
||||
; CHECK-NEXT: ushll2.4s v2, v0, #0
|
||||
; CHECK-NEXT: ushll.4s v0, v0, #0
|
||||
; CHECK-NEXT: ushll2.2d v3, v2, #0
|
||||
; CHECK-NEXT: ushll2.2d v1, v0, #0
|
||||
; CHECK-NEXT: ushll.2d v2, v2, #0
|
||||
; CHECK-NEXT: ushll.2d v0, v0, #0
|
||||
; CHECK-NEXT: ret
|
||||
;
|
||||
%r = zext <8 x i8> %v0 to <8 x i64>
|
||||
ret <8 x i64> %r
|
||||
}
|
||||
|
||||
define <8 x i64> @sext_v8i8_to_v8i64(<8 x i8> %v0) nounwind {
|
||||
; CHECK-LABEL: sext_v8i8_to_v8i64:
|
||||
; CHECK-NEXT: sshll.8h v0, v0, #0
|
||||
; CHECK-NEXT: sshll2.4s v2, v0, #0
|
||||
; CHECK-NEXT: sshll.4s v0, v0, #0
|
||||
; CHECK-NEXT: sshll2.2d v3, v2, #0
|
||||
; CHECK-NEXT: sshll2.2d v1, v0, #0
|
||||
; CHECK-NEXT: sshll.2d v2, v2, #0
|
||||
; CHECK-NEXT: sshll.2d v0, v0, #0
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: sshll.8h v0, v0, #0
|
||||
; CHECK-NEXT: sshll2.4s v2, v0, #0
|
||||
; CHECK-NEXT: sshll.4s v0, v0, #0
|
||||
; CHECK-NEXT: sshll2.2d v3, v2, #0
|
||||
; CHECK-NEXT: sshll2.2d v1, v0, #0
|
||||
; CHECK-NEXT: sshll.2d v2, v2, #0
|
||||
; CHECK-NEXT: sshll.2d v0, v0, #0
|
||||
; CHECK-NEXT: ret
|
||||
;
|
||||
%r = sext <8 x i8> %v0 to <8 x i64>
|
||||
ret <8 x i64> %r
|
||||
}
|
||||
|
|
@ -207,7 +222,65 @@ define <8 x i64> @sext_v8i8_to_v8i64(<8 x i8> %v0) nounwind {
|
|||
|
||||
define <32 x i8> @zext_v32i1(<32 x i1> %arg) {
|
||||
; CHECK-LABEL: zext_v32i1:
|
||||
; CHECK: and.16b v0, v0, v2
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldr w8, [sp, #64]
|
||||
; CHECK-NEXT: ldr w9, [sp, #72]
|
||||
; CHECK-NEXT: ldr w10, [sp, #80]
|
||||
; CHECK-NEXT: fmov s0, w0
|
||||
; CHECK-NEXT: ldr w11, [sp, #88]
|
||||
; CHECK-NEXT: mov.b v0[1], w1
|
||||
; CHECK-NEXT: ldr w12, [sp, #96]
|
||||
; CHECK-NEXT: fmov s1, w8
|
||||
; CHECK-NEXT: mov.b v0[2], w2
|
||||
; CHECK-NEXT: ldr w8, [sp, #104]
|
||||
; CHECK-NEXT: mov.b v1[1], w9
|
||||
; CHECK-NEXT: mov.b v0[3], w3
|
||||
; CHECK-NEXT: ldr w13, [sp, #112]
|
||||
; CHECK-NEXT: mov.b v1[2], w10
|
||||
; CHECK-NEXT: mov.b v0[4], w4
|
||||
; CHECK-NEXT: ldr w9, [sp, #120]
|
||||
; CHECK-NEXT: mov.b v1[3], w11
|
||||
; CHECK-NEXT: ldr w11, [sp]
|
||||
; CHECK-NEXT: mov.b v0[5], w5
|
||||
; CHECK-NEXT: mov.b v1[4], w12
|
||||
; CHECK-NEXT: ldr w12, [sp, #8]
|
||||
; CHECK-NEXT: ldr w14, [sp, #128]
|
||||
; CHECK-NEXT: mov.b v0[6], w6
|
||||
; CHECK-NEXT: mov.b v1[5], w8
|
||||
; CHECK-NEXT: ldr w8, [sp, #16]
|
||||
; CHECK-NEXT: ldr w10, [sp, #136]
|
||||
; CHECK-NEXT: mov.b v0[7], w7
|
||||
; CHECK-NEXT: mov.b v1[6], w13
|
||||
; CHECK-NEXT: ldr w13, [sp, #24]
|
||||
; CHECK-NEXT: ldr w15, [sp, #144]
|
||||
; CHECK-NEXT: mov.b v0[8], w11
|
||||
; CHECK-NEXT: mov.b v1[7], w9
|
||||
; CHECK-NEXT: ldr w9, [sp, #32]
|
||||
; CHECK-NEXT: ldr w16, [sp, #152]
|
||||
; CHECK-NEXT: mov.b v0[9], w12
|
||||
; CHECK-NEXT: ldr w11, [sp, #160]
|
||||
; CHECK-NEXT: mov.b v0[10], w8
|
||||
; CHECK-NEXT: mov.b v1[8], w14
|
||||
; CHECK-NEXT: ldr w12, [sp, #168]
|
||||
; CHECK-NEXT: mov.b v0[11], w13
|
||||
; CHECK-NEXT: ldr w14, [sp, #40]
|
||||
; CHECK-NEXT: mov.b v1[9], w10
|
||||
; CHECK-NEXT: ldr w8, [sp, #176]
|
||||
; CHECK-NEXT: mov.b v0[12], w9
|
||||
; CHECK-NEXT: ldr w9, [sp, #48]
|
||||
; CHECK-NEXT: mov.b v1[10], w15
|
||||
; CHECK-NEXT: ldr w13, [sp, #184]
|
||||
; CHECK-NEXT: ldr w10, [sp, #56]
|
||||
; CHECK-NEXT: mov.b v1[11], w16
|
||||
; CHECK-NEXT: mov.b v1[12], w11
|
||||
; CHECK-NEXT: mov.b v0[13], w14
|
||||
; CHECK-NEXT: mov.b v1[13], w12
|
||||
; CHECK-NEXT: mov.b v0[14], w9
|
||||
; CHECK-NEXT: mov.b v1[14], w8
|
||||
; CHECK-NEXT: movi.16b v2, #1
|
||||
; CHECK-NEXT: mov.b v0[15], w10
|
||||
; CHECK-NEXT: mov.b v1[15], w13
|
||||
; CHECK-NEXT: and.16b v0, v0, v2
|
||||
; CHECK-NEXT: and.16b v1, v1, v2
|
||||
; CHECK-NEXT: ret
|
||||
%res = zext <32 x i1> %arg to <32 x i8>
|
||||
|
|
@ -216,54 +289,358 @@ define <32 x i8> @zext_v32i1(<32 x i1> %arg) {
|
|||
|
||||
define <32 x i8> @sext_v32i1(<32 x i1> %arg) {
|
||||
; CHECK-LABEL: sext_v32i1:
|
||||
; CHECK: shl.16b v0, v0, #7
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldr w8, [sp, #64]
|
||||
; CHECK-NEXT: ldr w9, [sp, #72]
|
||||
; CHECK-NEXT: ldr w10, [sp, #80]
|
||||
; CHECK-NEXT: fmov s0, w0
|
||||
; CHECK-NEXT: ldr w11, [sp, #88]
|
||||
; CHECK-NEXT: mov.b v0[1], w1
|
||||
; CHECK-NEXT: ldr w12, [sp, #96]
|
||||
; CHECK-NEXT: fmov s1, w8
|
||||
; CHECK-NEXT: mov.b v0[2], w2
|
||||
; CHECK-NEXT: ldr w8, [sp, #104]
|
||||
; CHECK-NEXT: mov.b v1[1], w9
|
||||
; CHECK-NEXT: mov.b v0[3], w3
|
||||
; CHECK-NEXT: ldr w13, [sp, #112]
|
||||
; CHECK-NEXT: mov.b v1[2], w10
|
||||
; CHECK-NEXT: mov.b v0[4], w4
|
||||
; CHECK-NEXT: ldr w9, [sp, #120]
|
||||
; CHECK-NEXT: mov.b v1[3], w11
|
||||
; CHECK-NEXT: ldr w11, [sp]
|
||||
; CHECK-NEXT: mov.b v0[5], w5
|
||||
; CHECK-NEXT: mov.b v1[4], w12
|
||||
; CHECK-NEXT: ldr w12, [sp, #8]
|
||||
; CHECK-NEXT: ldr w14, [sp, #128]
|
||||
; CHECK-NEXT: mov.b v0[6], w6
|
||||
; CHECK-NEXT: mov.b v1[5], w8
|
||||
; CHECK-NEXT: ldr w8, [sp, #16]
|
||||
; CHECK-NEXT: ldr w10, [sp, #136]
|
||||
; CHECK-NEXT: mov.b v0[7], w7
|
||||
; CHECK-NEXT: mov.b v1[6], w13
|
||||
; CHECK-NEXT: ldr w13, [sp, #24]
|
||||
; CHECK-NEXT: ldr w15, [sp, #144]
|
||||
; CHECK-NEXT: mov.b v0[8], w11
|
||||
; CHECK-NEXT: mov.b v1[7], w9
|
||||
; CHECK-NEXT: ldr w9, [sp, #32]
|
||||
; CHECK-NEXT: ldr w16, [sp, #152]
|
||||
; CHECK-NEXT: mov.b v0[9], w12
|
||||
; CHECK-NEXT: ldr w11, [sp, #160]
|
||||
; CHECK-NEXT: mov.b v0[10], w8
|
||||
; CHECK-NEXT: mov.b v1[8], w14
|
||||
; CHECK-NEXT: ldr w12, [sp, #168]
|
||||
; CHECK-NEXT: mov.b v0[11], w13
|
||||
; CHECK-NEXT: ldr w14, [sp, #40]
|
||||
; CHECK-NEXT: mov.b v1[9], w10
|
||||
; CHECK-NEXT: ldr w8, [sp, #176]
|
||||
; CHECK-NEXT: mov.b v0[12], w9
|
||||
; CHECK-NEXT: ldr w9, [sp, #48]
|
||||
; CHECK-NEXT: mov.b v1[10], w15
|
||||
; CHECK-NEXT: ldr w13, [sp, #184]
|
||||
; CHECK-NEXT: ldr w10, [sp, #56]
|
||||
; CHECK-NEXT: mov.b v1[11], w16
|
||||
; CHECK-NEXT: mov.b v1[12], w11
|
||||
; CHECK-NEXT: mov.b v0[13], w14
|
||||
; CHECK-NEXT: mov.b v1[13], w12
|
||||
; CHECK-NEXT: mov.b v0[14], w9
|
||||
; CHECK-NEXT: mov.b v1[14], w8
|
||||
; CHECK-NEXT: mov.b v0[15], w10
|
||||
; CHECK-NEXT: mov.b v1[15], w13
|
||||
; CHECK-NEXT: shl.16b v0, v0, #7
|
||||
; CHECK-NEXT: shl.16b v1, v1, #7
|
||||
; CHECK-NEXT: sshr.16b v0, v0, #7
|
||||
; CHECK-NEXT: sshr.16b v1, v1, #7
|
||||
; CHECK-NEXT: ret
|
||||
;
|
||||
%res = sext <32 x i1> %arg to <32 x i8>
|
||||
ret <32 x i8> %res
|
||||
}
|
||||
|
||||
define <64 x i8> @zext_v64i1(<64 x i1> %arg) {
|
||||
; CHECK-LABEL: zext_v64i1:
|
||||
; CHECK: and.16b v0, v0, [[V4:v.+]]
|
||||
; CHECK-NEXT: and.16b v1, v1, [[V4]]
|
||||
; CHECK-NEXT: and.16b v2, v2, [[V4]]
|
||||
; CHECK-NEXT: and.16b v3, v3, [[V4]]
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldr w11, [sp, #64]
|
||||
; CHECK-NEXT: ldr w8, [sp, #320]
|
||||
; CHECK-NEXT: ldr w10, [sp, #192]
|
||||
; CHECK-NEXT: ldr w9, [sp, #328]
|
||||
; CHECK-NEXT: ldr w12, [sp, #336]
|
||||
; CHECK-NEXT: fmov s1, w11
|
||||
; CHECK-NEXT: ldr w11, [sp, #200]
|
||||
; CHECK-NEXT: fmov s3, w8
|
||||
; CHECK-NEXT: ldr w8, [sp, #344]
|
||||
; CHECK-NEXT: fmov s0, w0
|
||||
; CHECK-NEXT: fmov s2, w10
|
||||
; CHECK-NEXT: ldr w10, [sp, #352]
|
||||
; CHECK-NEXT: mov.b v0[1], w1
|
||||
; CHECK-NEXT: mov.b v3[1], w9
|
||||
; CHECK-NEXT: ldr w9, [sp, #360]
|
||||
; CHECK-NEXT: mov.b v0[2], w2
|
||||
; CHECK-NEXT: ldr w13, [sp, #72]
|
||||
; CHECK-NEXT: mov.b v2[1], w11
|
||||
; CHECK-NEXT: ldr w11, [sp, #368]
|
||||
; CHECK-NEXT: mov.b v3[2], w12
|
||||
; CHECK-NEXT: mov.b v0[3], w3
|
||||
; CHECK-NEXT: ldr w12, [sp, #376]
|
||||
; CHECK-NEXT: mov.b v3[3], w8
|
||||
; CHECK-NEXT: mov.b v0[4], w4
|
||||
; CHECK-NEXT: mov.b v3[4], w10
|
||||
; CHECK-NEXT: ldr w10, [sp]
|
||||
; CHECK-NEXT: mov.b v0[5], w5
|
||||
; CHECK-NEXT: ldr w14, [sp, #80]
|
||||
; CHECK-NEXT: mov.b v3[5], w9
|
||||
; CHECK-NEXT: ldr w9, [sp, #8]
|
||||
; CHECK-NEXT: mov.b v1[1], w13
|
||||
; CHECK-NEXT: ldr w13, [sp, #208]
|
||||
; CHECK-NEXT: mov.b v0[6], w6
|
||||
; CHECK-NEXT: ldr w15, [sp, #88]
|
||||
; CHECK-NEXT: mov.b v3[6], w11
|
||||
; CHECK-NEXT: ldr w11, [sp, #16]
|
||||
; CHECK-NEXT: mov.b v0[7], w7
|
||||
; CHECK-NEXT: ldr w16, [sp, #96]
|
||||
; CHECK-NEXT: mov.b v3[7], w12
|
||||
; CHECK-NEXT: ldr w12, [sp, #24]
|
||||
; CHECK-NEXT: mov.b v0[8], w10
|
||||
; CHECK-NEXT: ldr w10, [sp, #104]
|
||||
; CHECK-NEXT: mov.b v1[2], w14
|
||||
; CHECK-NEXT: ldr w14, [sp, #216]
|
||||
; CHECK-NEXT: mov.b v0[9], w9
|
||||
; CHECK-NEXT: ldr w9, [sp, #112]
|
||||
; CHECK-NEXT: mov.b v2[2], w13
|
||||
; CHECK-NEXT: ldr w13, [sp, #384]
|
||||
; CHECK-NEXT: mov.b v1[3], w15
|
||||
; CHECK-NEXT: ldr w15, [sp, #224]
|
||||
; CHECK-NEXT: mov.b v0[10], w11
|
||||
; CHECK-NEXT: ldr w11, [sp, #120]
|
||||
; CHECK-NEXT: mov.b v1[4], w16
|
||||
; CHECK-NEXT: ldr w16, [sp, #232]
|
||||
; CHECK-NEXT: mov.b v0[11], w12
|
||||
; CHECK-NEXT: ldr w12, [sp, #128]
|
||||
; CHECK-NEXT: mov.b v1[5], w10
|
||||
; CHECK-NEXT: ldr w10, [sp, #240]
|
||||
; CHECK-NEXT: mov.b v2[3], w14
|
||||
; CHECK-NEXT: mov.b v1[6], w9
|
||||
; CHECK-NEXT: ldr w9, [sp, #248]
|
||||
; CHECK-NEXT: ldr w8, [sp, #392]
|
||||
; CHECK-NEXT: mov.b v2[4], w15
|
||||
; CHECK-NEXT: mov.b v1[7], w11
|
||||
; CHECK-NEXT: ldr w11, [sp, #256]
|
||||
; CHECK-NEXT: mov.b v3[8], w13
|
||||
; CHECK-NEXT: ldr w13, [sp, #32]
|
||||
; CHECK-NEXT: ldr w14, [sp, #400]
|
||||
; CHECK-NEXT: mov.b v2[5], w16
|
||||
; CHECK-NEXT: mov.b v1[8], w12
|
||||
; CHECK-NEXT: ldr w12, [sp, #264]
|
||||
; CHECK-NEXT: ldr w15, [sp, #408]
|
||||
; CHECK-NEXT: mov.b v2[6], w10
|
||||
; CHECK-NEXT: mov.b v2[7], w9
|
||||
; CHECK-NEXT: mov.b v2[8], w11
|
||||
; CHECK-NEXT: mov.b v0[12], w13
|
||||
; CHECK-NEXT: ldr w13, [sp, #136]
|
||||
; CHECK-NEXT: mov.b v3[9], w8
|
||||
; CHECK-NEXT: ldr w8, [sp, #40]
|
||||
; CHECK-NEXT: mov.b v2[9], w12
|
||||
; CHECK-NEXT: ldr w12, [sp, #272]
|
||||
; CHECK-NEXT: mov.b v3[10], w14
|
||||
; CHECK-NEXT: ldr w14, [sp, #48]
|
||||
; CHECK-NEXT: mov.b v3[11], w15
|
||||
; CHECK-NEXT: ldr w15, [sp, #56]
|
||||
; CHECK-NEXT: ldr w16, [sp, #416]
|
||||
; CHECK-NEXT: mov.b v1[9], w13
|
||||
; CHECK-NEXT: ldr w13, [sp, #280]
|
||||
; CHECK-NEXT: mov.b v0[13], w8
|
||||
; CHECK-NEXT: ldr w8, [sp, #144]
|
||||
; CHECK-NEXT: mov.b v2[10], w12
|
||||
; CHECK-NEXT: ldr w12, [sp, #288]
|
||||
; CHECK-NEXT: mov.b v0[14], w14
|
||||
; CHECK-NEXT: ldr w14, [sp, #152]
|
||||
; CHECK-NEXT: mov.b v0[15], w15
|
||||
; CHECK-NEXT: ldr w15, [sp, #160]
|
||||
; CHECK-NEXT: ldr w10, [sp, #424]
|
||||
; CHECK-NEXT: mov.b v1[10], w8
|
||||
; CHECK-NEXT: ldr w8, [sp, #296]
|
||||
; CHECK-NEXT: mov.b v2[11], w13
|
||||
; CHECK-NEXT: mov.b v3[12], w16
|
||||
; CHECK-NEXT: ldr w16, [sp, #168]
|
||||
; CHECK-NEXT: ldr w9, [sp, #432]
|
||||
; CHECK-NEXT: ldr w13, [sp, #304]
|
||||
; CHECK-NEXT: mov.b v1[11], w14
|
||||
; CHECK-NEXT: mov.b v2[12], w12
|
||||
; CHECK-NEXT: ldr w12, [sp, #176]
|
||||
; CHECK-NEXT: ldr w11, [sp, #440]
|
||||
; CHECK-NEXT: ldr w14, [sp, #312]
|
||||
; CHECK-NEXT: mov.b v1[12], w15
|
||||
; CHECK-NEXT: ldr w15, [sp, #184]
|
||||
; CHECK-NEXT: mov.b v3[13], w10
|
||||
; CHECK-NEXT: mov.b v2[13], w8
|
||||
; CHECK-NEXT: mov.b v1[13], w16
|
||||
; CHECK-NEXT: mov.b v3[14], w9
|
||||
; CHECK-NEXT: mov.b v2[14], w13
|
||||
; CHECK-NEXT: mov.b v1[14], w12
|
||||
; CHECK-NEXT: movi.16b v4, #1
|
||||
; CHECK-NEXT: mov.b v3[15], w11
|
||||
; CHECK-NEXT: mov.b v2[15], w14
|
||||
; CHECK-NEXT: mov.b v1[15], w15
|
||||
; CHECK-NEXT: and.16b v0, v0, v4
|
||||
; CHECK-NEXT: and.16b v1, v1, v4
|
||||
; CHECK-NEXT: and.16b v2, v2, v4
|
||||
; CHECK-NEXT: and.16b v3, v3, v4
|
||||
; CHECK-NEXT: ret
|
||||
;
|
||||
%res = zext <64 x i1> %arg to <64 x i8>
|
||||
ret <64 x i8> %res
|
||||
}
|
||||
|
||||
define <64 x i8> @sext_v64i1(<64 x i1> %arg) {
|
||||
; CHECK-LABEL: sext_v64i1:
|
||||
; CHECK: shl.16b v0, v0, #7
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldr w11, [sp, #64]
|
||||
; CHECK-NEXT: ldr w8, [sp, #320]
|
||||
; CHECK-NEXT: ldr w10, [sp, #192]
|
||||
; CHECK-NEXT: ldr w9, [sp, #328]
|
||||
; CHECK-NEXT: ldr w12, [sp, #336]
|
||||
; CHECK-NEXT: fmov s3, w11
|
||||
; CHECK-NEXT: ldr w11, [sp, #200]
|
||||
; CHECK-NEXT: fmov s1, w8
|
||||
; CHECK-NEXT: ldr w8, [sp, #344]
|
||||
; CHECK-NEXT: fmov s0, w0
|
||||
; CHECK-NEXT: fmov s2, w10
|
||||
; CHECK-NEXT: ldr w10, [sp, #352]
|
||||
; CHECK-NEXT: mov.b v0[1], w1
|
||||
; CHECK-NEXT: mov.b v1[1], w9
|
||||
; CHECK-NEXT: ldr w9, [sp, #360]
|
||||
; CHECK-NEXT: mov.b v0[2], w2
|
||||
; CHECK-NEXT: ldr w13, [sp, #72]
|
||||
; CHECK-NEXT: mov.b v2[1], w11
|
||||
; CHECK-NEXT: ldr w11, [sp, #368]
|
||||
; CHECK-NEXT: mov.b v1[2], w12
|
||||
; CHECK-NEXT: mov.b v0[3], w3
|
||||
; CHECK-NEXT: ldr w12, [sp, #376]
|
||||
; CHECK-NEXT: mov.b v1[3], w8
|
||||
; CHECK-NEXT: mov.b v0[4], w4
|
||||
; CHECK-NEXT: mov.b v1[4], w10
|
||||
; CHECK-NEXT: ldr w10, [sp]
|
||||
; CHECK-NEXT: mov.b v0[5], w5
|
||||
; CHECK-NEXT: ldr w14, [sp, #80]
|
||||
; CHECK-NEXT: mov.b v1[5], w9
|
||||
; CHECK-NEXT: ldr w9, [sp, #8]
|
||||
; CHECK-NEXT: mov.b v3[1], w13
|
||||
; CHECK-NEXT: ldr w13, [sp, #208]
|
||||
; CHECK-NEXT: mov.b v0[6], w6
|
||||
; CHECK-NEXT: ldr w15, [sp, #88]
|
||||
; CHECK-NEXT: mov.b v1[6], w11
|
||||
; CHECK-NEXT: ldr w11, [sp, #16]
|
||||
; CHECK-NEXT: mov.b v0[7], w7
|
||||
; CHECK-NEXT: ldr w16, [sp, #96]
|
||||
; CHECK-NEXT: mov.b v1[7], w12
|
||||
; CHECK-NEXT: ldr w12, [sp, #24]
|
||||
; CHECK-NEXT: mov.b v0[8], w10
|
||||
; CHECK-NEXT: ldr w10, [sp, #104]
|
||||
; CHECK-NEXT: mov.b v3[2], w14
|
||||
; CHECK-NEXT: ldr w14, [sp, #216]
|
||||
; CHECK-NEXT: mov.b v0[9], w9
|
||||
; CHECK-NEXT: ldr w9, [sp, #112]
|
||||
; CHECK-NEXT: mov.b v2[2], w13
|
||||
; CHECK-NEXT: ldr w13, [sp, #384]
|
||||
; CHECK-NEXT: mov.b v3[3], w15
|
||||
; CHECK-NEXT: ldr w15, [sp, #224]
|
||||
; CHECK-NEXT: mov.b v0[10], w11
|
||||
; CHECK-NEXT: ldr w11, [sp, #120]
|
||||
; CHECK-NEXT: mov.b v3[4], w16
|
||||
; CHECK-NEXT: ldr w16, [sp, #232]
|
||||
; CHECK-NEXT: mov.b v0[11], w12
|
||||
; CHECK-NEXT: ldr w12, [sp, #128]
|
||||
; CHECK-NEXT: mov.b v3[5], w10
|
||||
; CHECK-NEXT: ldr w10, [sp, #240]
|
||||
; CHECK-NEXT: mov.b v2[3], w14
|
||||
; CHECK-NEXT: mov.b v3[6], w9
|
||||
; CHECK-NEXT: ldr w9, [sp, #248]
|
||||
; CHECK-NEXT: ldr w8, [sp, #392]
|
||||
; CHECK-NEXT: mov.b v2[4], w15
|
||||
; CHECK-NEXT: mov.b v3[7], w11
|
||||
; CHECK-NEXT: ldr w11, [sp, #256]
|
||||
; CHECK-NEXT: mov.b v1[8], w13
|
||||
; CHECK-NEXT: ldr w13, [sp, #32]
|
||||
; CHECK-NEXT: ldr w14, [sp, #400]
|
||||
; CHECK-NEXT: mov.b v2[5], w16
|
||||
; CHECK-NEXT: mov.b v3[8], w12
|
||||
; CHECK-NEXT: ldr w12, [sp, #264]
|
||||
; CHECK-NEXT: ldr w15, [sp, #408]
|
||||
; CHECK-NEXT: mov.b v2[6], w10
|
||||
; CHECK-NEXT: mov.b v2[7], w9
|
||||
; CHECK-NEXT: mov.b v2[8], w11
|
||||
; CHECK-NEXT: mov.b v0[12], w13
|
||||
; CHECK-NEXT: ldr w13, [sp, #136]
|
||||
; CHECK-NEXT: mov.b v1[9], w8
|
||||
; CHECK-NEXT: ldr w8, [sp, #40]
|
||||
; CHECK-NEXT: mov.b v2[9], w12
|
||||
; CHECK-NEXT: ldr w12, [sp, #272]
|
||||
; CHECK-NEXT: mov.b v1[10], w14
|
||||
; CHECK-NEXT: ldr w14, [sp, #48]
|
||||
; CHECK-NEXT: mov.b v1[11], w15
|
||||
; CHECK-NEXT: ldr w15, [sp, #56]
|
||||
; CHECK-NEXT: ldr w16, [sp, #416]
|
||||
; CHECK-NEXT: mov.b v3[9], w13
|
||||
; CHECK-NEXT: ldr w13, [sp, #280]
|
||||
; CHECK-NEXT: mov.b v0[13], w8
|
||||
; CHECK-NEXT: ldr w8, [sp, #144]
|
||||
; CHECK-NEXT: mov.b v2[10], w12
|
||||
; CHECK-NEXT: ldr w12, [sp, #288]
|
||||
; CHECK-NEXT: mov.b v0[14], w14
|
||||
; CHECK-NEXT: ldr w14, [sp, #152]
|
||||
; CHECK-NEXT: mov.b v0[15], w15
|
||||
; CHECK-NEXT: ldr w15, [sp, #160]
|
||||
; CHECK-NEXT: ldr w10, [sp, #424]
|
||||
; CHECK-NEXT: mov.b v3[10], w8
|
||||
; CHECK-NEXT: ldr w8, [sp, #296]
|
||||
; CHECK-NEXT: mov.b v2[11], w13
|
||||
; CHECK-NEXT: mov.b v1[12], w16
|
||||
; CHECK-NEXT: ldr w16, [sp, #168]
|
||||
; CHECK-NEXT: ldr w9, [sp, #432]
|
||||
; CHECK-NEXT: ldr w13, [sp, #304]
|
||||
; CHECK-NEXT: mov.b v3[11], w14
|
||||
; CHECK-NEXT: mov.b v2[12], w12
|
||||
; CHECK-NEXT: ldr w12, [sp, #176]
|
||||
; CHECK-NEXT: ldr w11, [sp, #440]
|
||||
; CHECK-NEXT: ldr w14, [sp, #312]
|
||||
; CHECK-NEXT: mov.b v3[12], w15
|
||||
; CHECK-NEXT: ldr w15, [sp, #184]
|
||||
; CHECK-NEXT: mov.b v1[13], w10
|
||||
; CHECK-NEXT: mov.b v2[13], w8
|
||||
; CHECK-NEXT: mov.b v3[13], w16
|
||||
; CHECK-NEXT: mov.b v1[14], w9
|
||||
; CHECK-NEXT: mov.b v2[14], w13
|
||||
; CHECK-NEXT: mov.b v3[14], w12
|
||||
; CHECK-NEXT: mov.b v1[15], w11
|
||||
; CHECK-NEXT: mov.b v2[15], w14
|
||||
; CHECK-NEXT: mov.b v3[15], w15
|
||||
; CHECK-NEXT: shl.16b v0, v0, #7
|
||||
; CHECK-NEXT: shl.16b v3, v3, #7
|
||||
; CHECK-NEXT: shl.16b v2, v2, #7
|
||||
; CHECK-NEXT: shl.16b [[V4:v.+]], v1, #7
|
||||
; CHECK-NEXT: shl.16b v4, v1, #7
|
||||
; CHECK-NEXT: sshr.16b v0, v0, #7
|
||||
; CHECK-NEXT: sshr.16b v1, v3, #7
|
||||
; CHECK-NEXT: sshr.16b v2, v2, #7
|
||||
; CHECK-NEXT: sshr.16b v3, [[V4]], #7
|
||||
; CHECK-NEXT: sshr.16b v3, v4, #7
|
||||
; CHECK-NEXT: ret
|
||||
;
|
||||
%res = sext <64 x i1> %arg to <64 x i8>
|
||||
ret <64 x i8> %res
|
||||
}
|
||||
|
||||
define <1 x i128> @sext_v1x64(<1 x i64> %arg) {
|
||||
; CHECK-LABEL: sext_v1x64:
|
||||
; CHECK-NEXT: .cfi_startproc
|
||||
; CHECK-NEXT: fmov x8, d0
|
||||
; CHECK-NEXT: asr x1, x8, #63
|
||||
; X0 & X1 are the real return registers, SDAG messes with v0 too for unknown reasons.
|
||||
; CHECK: {{(mov.d v0[1], x1)?}}
|
||||
; CHECK: fmov x0, d0
|
||||
; CHECK: ret
|
||||
; CHECKDAG-LABEL: sext_v1x64:
|
||||
; CHECKDAG: // %bb.0:
|
||||
; CHECKDAG-NEXT: // kill: def $d0 killed $d0 def $q0
|
||||
; CHECKDAG-NEXT: fmov x8, d0
|
||||
; CHECKDAG-NEXT: asr x1, x8, #63
|
||||
; CHECKDAG-NEXT: mov.d v0[1], x1
|
||||
; CHECKDAG-NEXT: fmov x0, d0
|
||||
; CHECKDAG-NEXT: ret
|
||||
;
|
||||
; FALLBACK-LABEL: sext_v1x64:
|
||||
; FALLBACK: // %bb.0:
|
||||
; FALLBACK-NEXT: fmov x8, d0
|
||||
; FALLBACK-NEXT: asr x1, x8, #63
|
||||
; FALLBACK-NEXT: fmov x0, d0
|
||||
; FALLBACK-NEXT: ret
|
||||
%res = sext <1 x i64> %arg to <1 x i128>
|
||||
ret <1 x i128> %res
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,10 +1,12 @@
|
|||
; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -disable-post-ra | FileCheck %s
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -mtriple=arm64-none-eabi | FileCheck %s
|
||||
|
||||
define void @bar(<8 x i16> %arg, <8 x i8>* %p) nounwind {
|
||||
; CHECK-LABEL: bar:
|
||||
; CHECK: xtn.8b v[[REG:[0-9]+]], v0
|
||||
; CHECK-NEXT: str d[[REG]], [x0]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: xtn v0.8b, v0.8h
|
||||
; CHECK-NEXT: str d0, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%tmp = trunc <8 x i16> %arg to <8 x i8>
|
||||
store <8 x i8> %tmp, <8 x i8>* %p, align 8
|
||||
ret void
|
||||
|
|
@ -15,15 +17,14 @@ define void @bar(<8 x i16> %arg, <8 x i8>* %p) nounwind {
|
|||
@zptr32 = common global i32* null, align 8
|
||||
|
||||
define void @fct32(i32 %arg, i64 %var) {
|
||||
; CHECK: fct32
|
||||
; CHECK: adrp [[GLOBALPAGE:x[0-9]+]], _zptr32@GOTPAGE
|
||||
; CHECK: ldr [[GLOBALOFF:x[0-9]+]], {{\[}}[[GLOBALPAGE]], _zptr32@GOTPAGEOFF]
|
||||
; CHECK: ldr [[GLOBALADDR:x[0-9]+]], {{\[}}[[GLOBALOFF]]]
|
||||
; w0 is %arg
|
||||
; CHECK-NEXT: sub w[[OFFSETREGNUM:[0-9]+]], w0, #1
|
||||
; w1 is %var truncated
|
||||
; CHECK-NEXT: str w1, {{\[}}[[GLOBALADDR]], w[[OFFSETREGNUM]], sxtw #2]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK-LABEL: fct32:
|
||||
; CHECK: // %bb.0: // %bb
|
||||
; CHECK-NEXT: adrp x8, :got:zptr32
|
||||
; CHECK-NEXT: ldr x8, [x8, :got_lo12:zptr32]
|
||||
; CHECK-NEXT: sub w9, w0, #1
|
||||
; CHECK-NEXT: ldr x8, [x8]
|
||||
; CHECK-NEXT: str w1, [x8, w9, sxtw #2]
|
||||
; CHECK-NEXT: ret
|
||||
bb:
|
||||
%.pre37 = load i32*, i32** @zptr32, align 8
|
||||
%dec = add nsw i32 %arg, -1
|
||||
|
|
@ -35,15 +36,14 @@ bb:
|
|||
}
|
||||
|
||||
define void @fct16(i32 %arg, i64 %var) {
|
||||
; CHECK: fct16
|
||||
; CHECK: adrp [[GLOBALPAGE:x[0-9]+]], _zptr16@GOTPAGE
|
||||
; CHECK: ldr [[GLOBALOFF:x[0-9]+]], {{\[}}[[GLOBALPAGE]], _zptr16@GOTPAGEOFF]
|
||||
; CHECK: ldr [[GLOBALADDR:x[0-9]+]], {{\[}}[[GLOBALOFF]]]
|
||||
; w0 is %arg
|
||||
; CHECK-NEXT: sub w[[OFFSETREGNUM:[0-9]+]], w0, #1
|
||||
; w1 is %var truncated
|
||||
; CHECK-NEXT: strh w1, {{\[}}[[GLOBALADDR]], w[[OFFSETREGNUM]], sxtw #1]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK-LABEL: fct16:
|
||||
; CHECK: // %bb.0: // %bb
|
||||
; CHECK-NEXT: adrp x8, :got:zptr16
|
||||
; CHECK-NEXT: ldr x8, [x8, :got_lo12:zptr16]
|
||||
; CHECK-NEXT: sub w9, w0, #1
|
||||
; CHECK-NEXT: ldr x8, [x8]
|
||||
; CHECK-NEXT: strh w1, [x8, w9, sxtw #1]
|
||||
; CHECK-NEXT: ret
|
||||
bb:
|
||||
%.pre37 = load i16*, i16** @zptr16, align 8
|
||||
%dec = add nsw i32 %arg, -1
|
||||
|
|
@ -55,15 +55,14 @@ bb:
|
|||
}
|
||||
|
||||
define void @fct8(i32 %arg, i64 %var) {
|
||||
; CHECK: fct8
|
||||
; CHECK: adrp [[GLOBALPAGE:x[0-9]+]], _zptr8@GOTPAGE
|
||||
; CHECK: ldr [[GLOBALOFF:x[0-9]+]], {{\[}}[[GLOBALPAGE]], _zptr8@GOTPAGEOFF]
|
||||
; CHECK: ldr [[BASEADDR:x[0-9]+]], {{\[}}[[GLOBALOFF]]]
|
||||
; w0 is %arg
|
||||
; CHECK-NEXT: add [[ADDR:x[0-9]+]], [[BASEADDR]], w0, sxtw
|
||||
; w1 is %var truncated
|
||||
; CHECK-NEXT: sturb w1, {{\[}}[[ADDR]], #-1]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK-LABEL: fct8:
|
||||
; CHECK: // %bb.0: // %bb
|
||||
; CHECK-NEXT: adrp x8, :got:zptr8
|
||||
; CHECK-NEXT: ldr x8, [x8, :got_lo12:zptr8]
|
||||
; CHECK-NEXT: ldr x8, [x8]
|
||||
; CHECK-NEXT: add x8, x8, w0, sxtw
|
||||
; CHECK-NEXT: sturb w1, [x8, #-1]
|
||||
; CHECK-NEXT: ret
|
||||
bb:
|
||||
%.pre37 = load i8*, i8** @zptr8, align 8
|
||||
%dec = add nsw i32 %arg, -1
|
||||
|
|
|
|||
Loading…
Reference in New Issue