From b72ca799823e97b94ac0144bb87c094fb2db7324 Mon Sep 17 00:00:00 2001 From: "Kazushi (Jam) Marukawa" Date: Fri, 8 Jan 2021 20:29:42 +0900 Subject: [PATCH] [VE] Support intrinsic to isnert/extract_subreg of v512i1 Support insert/extract_subreg intrinsic instructions for v512i1 registers and add regression tests. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D94298 --- llvm/include/llvm/IR/IntrinsicsVE.td | 18 ++++++++++ llvm/lib/Target/VE/VEInstrIntrinsicVL.td | 13 ++++++++ llvm/test/CodeGen/VE/VELIntrinsics/extract.ll | 33 +++++++++++++++++++ llvm/test/CodeGen/VE/VELIntrinsics/insert.ll | 32 ++++++++++++++++++ 4 files changed, 96 insertions(+) create mode 100644 llvm/test/CodeGen/VE/VELIntrinsics/extract.ll create mode 100644 llvm/test/CodeGen/VE/VELIntrinsics/insert.ll diff --git a/llvm/include/llvm/IR/IntrinsicsVE.td b/llvm/include/llvm/IR/IntrinsicsVE.td index 4e682eee7cc2..be4bccef0cc1 100644 --- a/llvm/include/llvm/IR/IntrinsicsVE.td +++ b/llvm/include/llvm/IR/IntrinsicsVE.td @@ -11,6 +11,24 @@ let TargetPrefix = "ve" in { def int_ve_vl_pack_f32a : GCCBuiltin<"__builtin_ve_vl_pack_f32a">, Intrinsic<[llvm_i64_ty], [llvm_ptr_ty], [IntrReadMem]>; + + def int_ve_vl_extract_vm512u : + GCCBuiltin<"__builtin_ve_vl_extract_vm512u">, + Intrinsic<[LLVMType], [LLVMType], [IntrNoMem]>; + + def int_ve_vl_extract_vm512l : + GCCBuiltin<"__builtin_ve_vl_extract_vm512l">, + Intrinsic<[LLVMType], [LLVMType], [IntrNoMem]>; + + def int_ve_vl_insert_vm512u : + GCCBuiltin<"__builtin_ve_vl_insert_vm512u">, + Intrinsic<[LLVMType], [LLVMType, LLVMType], + [IntrNoMem]>; + + def int_ve_vl_insert_vm512l : + GCCBuiltin<"__builtin_ve_vl_insert_vm512l">, + Intrinsic<[LLVMType], [LLVMType, LLVMType], + [IntrNoMem]>; } // Define intrinsics automatically generated diff --git a/llvm/lib/Target/VE/VEInstrIntrinsicVL.td b/llvm/lib/Target/VE/VEInstrIntrinsicVL.td index 3525484af108..9ccfbe1ea42e 100644 --- a/llvm/lib/Target/VE/VEInstrIntrinsicVL.td +++ b/llvm/lib/Target/VE/VEInstrIntrinsicVL.td @@ -17,6 +17,19 @@ def : Pat<(i64 (int_ve_vl_pack_f32a ADDRrii:$addr)), !add(32, 64)), 0, (HI32 (i64 0x0000000100000001))))>; +// The extract/insert patterns. +def : Pat<(v256i1 (int_ve_vl_extract_vm512u v512i1:$vm)), + (EXTRACT_SUBREG v512i1:$vm, sub_vm_even)>; + +def : Pat<(v256i1 (int_ve_vl_extract_vm512l v512i1:$vm)), + (EXTRACT_SUBREG v512i1:$vm, sub_vm_odd)>; + +def : Pat<(v512i1 (int_ve_vl_insert_vm512u v512i1:$vmx, v256i1:$vmy)), + (INSERT_SUBREG v512i1:$vmx, v256i1:$vmy, sub_vm_even)>; + +def : Pat<(v512i1 (int_ve_vl_insert_vm512l v512i1:$vmx, v256i1:$vmy)), + (INSERT_SUBREG v512i1:$vmx, v256i1:$vmy, sub_vm_odd)>; + // LSV patterns. def : Pat<(int_ve_vl_lsv_vvss v256f64:$pt, i32:$sy, i64:$sz), (LSVrr_v (i2l i32:$sy), i64:$sz, v256f64:$pt)>; diff --git a/llvm/test/CodeGen/VE/VELIntrinsics/extract.ll b/llvm/test/CodeGen/VE/VELIntrinsics/extract.ll new file mode 100644 index 000000000000..0e69448d7421 --- /dev/null +++ b/llvm/test/CodeGen/VE/VELIntrinsics/extract.ll @@ -0,0 +1,33 @@ +; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s + +;;; Test extract intrinsic instructions +;;; +;;; Note: +;;; We test extract_vm512u and extract_vm512l pseudo instructions. + +; Function Attrs: nounwind readnone +define fastcc <256 x i1> @extract_vm512u(<512 x i1> %0) { +; CHECK-LABEL: extract_vm512u: +; CHECK: # %bb.0: +; CHECK-NEXT: andm %vm1, %vm0, %vm2 +; CHECK-NEXT: b.l.t (, %s10) + %2 = tail call <256 x i1> @llvm.ve.vl.extract.vm512u(<512 x i1> %0) + ret <256 x i1> %2 +} + +; Function Attrs: nounwind readnone +declare <256 x i1> @llvm.ve.vl.extract.vm512u(<512 x i1>) + +; Function Attrs: nounwind readnone +define fastcc <256 x i1> @extract_vm512l(<512 x i1> %0) { +; CHECK-LABEL: extract_vm512l: +; CHECK: # %bb.0: +; CHECK-NEXT: andm %vm0, %vm0, %vm2 +; CHECK-NEXT: andm %vm1, %vm0, %vm3 +; CHECK-NEXT: b.l.t (, %s10) + %2 = tail call <256 x i1> @llvm.ve.vl.extract.vm512l(<512 x i1> %0) + ret <256 x i1> %2 +} + +; Function Attrs: nounwind readnone +declare <256 x i1> @llvm.ve.vl.extract.vm512l(<512 x i1>) diff --git a/llvm/test/CodeGen/VE/VELIntrinsics/insert.ll b/llvm/test/CodeGen/VE/VELIntrinsics/insert.ll new file mode 100644 index 000000000000..faa17be94f6e --- /dev/null +++ b/llvm/test/CodeGen/VE/VELIntrinsics/insert.ll @@ -0,0 +1,32 @@ +; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s + +;;; Test insert intrinsic instructions +;;; +;;; Note: +;;; We test insert_vm512u and insert_vm512l pseudo instructions. + +; Function Attrs: nounwind readnone +define fastcc <512 x i1> @insert_vm512u(<512 x i1> %0, <256 x i1> %1) { +; CHECK-LABEL: insert_vm512u: +; CHECK: # %bb.0: +; CHECK-NEXT: andm %vm2, %vm0, %vm4 +; CHECK-NEXT: b.l.t (, %s10) + %3 = tail call <512 x i1> @llvm.ve.vl.insert.vm512u(<512 x i1> %0, <256 x i1> %1) + ret <512 x i1> %3 +} + +; Function Attrs: nounwind readnone +declare <512 x i1> @llvm.ve.vl.insert.vm512u(<512 x i1>, <256 x i1>) + +; Function Attrs: nounwind readnone +define fastcc <512 x i1> @insert_vm512l(<512 x i1> %0, <256 x i1> %1) { +; CHECK-LABEL: insert_vm512l: +; CHECK: # %bb.0: +; CHECK-NEXT: andm %vm3, %vm0, %vm4 +; CHECK-NEXT: b.l.t (, %s10) + %3 = tail call <512 x i1> @llvm.ve.vl.insert.vm512l(<512 x i1> %0, <256 x i1> %1) + ret <512 x i1> %3 +} + +; Function Attrs: nounwind readnone +declare <512 x i1> @llvm.ve.vl.insert.vm512l(<512 x i1>, <256 x i1>)