maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

GlobalISel: Fix using wrong calling convention for callees 

This was taking the calling convention from the parent function,
instead of the callee. Avoids regressions in a future patch when the
caller and callee have different type breakdowns.

For some reason AArch64's lowerFormalArguments seems to intentionally
ignore the parent isVarArg.
This commit is contained in:
Matt Arsenault 2021-02-08 17:15:29 -05:00
parent 18ff7e045a
commit b72a23650f
6 changed files with 32 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
View File

@ -267,6 +267,7 @@ protected:
/// \return True if everything has succeeded, false otherwise.
bool handleAssignments(MachineIRBuilder &MIRBuilder,
SmallVectorImpl<ArgInfo> &Args, ValueHandler &Handler,
CallingConv::ID CallConv, bool IsVarArg,
Register ThisReturnReg = Register()) const;
bool handleAssignments(CCState &CCState,
SmallVectorImpl<CCValAssign> &ArgLocs,

4
llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
View File

@ -231,11 +231,13 @@ void CallLowering::unpackRegs(ArrayRef<Register> DstRegs, Register SrcReg,
bool CallLowering::handleAssignments(MachineIRBuilder &MIRBuilder,
SmallVectorImpl<ArgInfo> &Args,
ValueHandler &Handler,
CallingConv::ID CallConv, bool IsVarArg,
Register ThisReturnReg) const {
MachineFunction &MF = MIRBuilder.getMF();
const Function &F = MF.getFunction();
SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext());
CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, F.getContext());
return handleAssignments(CCInfo, ArgLocs, MIRBuilder, Args, Handler,
ThisReturnReg);
}

14
llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
View File

@ -409,7 +409,8 @@ bool AArch64CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
}
OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFn, AssignFn);
Success = handleAssignments(MIRBuilder, SplitArgs, Handler);
Success =
handleAssignments(MIRBuilder, SplitArgs, Handler, CC, F.isVarArg());
}
if (SwiftErrorVReg) {
@ -501,7 +502,8 @@ bool AArch64CallLowering::lowerFormalArguments(
TLI.CCAssignFnForCall(F.getCallingConv(), /*IsVarArg=*/false);
FormalArgHandler Handler(MIRBuilder, MRI, AssignFn);
if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
if (!handleAssignments(MIRBuilder, SplitArgs, Handler, F.getCallingConv(),
F.isVarArg()))
return false;
AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
@ -903,7 +905,7 @@ bool AArch64CallLowering::lowerTailCall(
// Do the actual argument marshalling.
OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFnFixed,
AssignFnVarArg, true, FPDiff);
if (!handleAssignments(MIRBuilder, OutArgs, Handler))
if (!handleAssignments(MIRBuilder, OutArgs, Handler, CalleeCC, Info.IsVarArg))
return false;
Mask = getMaskForArgs(OutArgs, Info, *TRI, MF);
@ -1015,7 +1017,8 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
// Do the actual argument marshalling.
OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFnFixed,
AssignFnVarArg, false);
if (!handleAssignments(MIRBuilder, OutArgs, Handler))
if (!handleAssignments(MIRBuilder, OutArgs, Handler, Info.CallConv,
Info.IsVarArg))
return false;
Mask = getMaskForArgs(OutArgs, Info, *TRI, MF);
@ -1050,6 +1053,7 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
RetAssignFn);
if (!handleAssignments(MIRBuilder, InArgs,
UsingReturnedArg ? ReturnedArgHandler : Handler,
Info.CallConv, Info.IsVarArg,
UsingReturnedArg ? OutArgs[0].Regs[0] : Register()))
return false;
}
@ -1075,4 +1079,4 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
bool AArch64CallLowering::isTypeIsValidForThisReturn(EVT Ty) const {
return Ty.getSizeInBits() == 64;
}
}

5
llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
View File

@ -513,7 +513,7 @@ bool AMDGPUCallLowering::lowerReturnVal(MachineIRBuilder &B,
CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(CC, F.isVarArg());
AMDGPUOutgoingValueHandler RetHandler(B, *MRI, Ret, AssignFn);
return handleAssignments(B, SplitRetInfos, RetHandler);
return handleAssignments(B, SplitRetInfos, RetHandler, CC, F.isVarArg());
}
bool AMDGPUCallLowering::lowerReturn(MachineIRBuilder &B, const Value *Val,
@ -1381,7 +1381,8 @@ bool AMDGPUCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
CCAssignFn *RetAssignFn = TLI.CCAssignFnForReturn(Info.CallConv,
Info.IsVarArg);
CallReturnHandler Handler(MIRBuilder, MRI, MIB, RetAssignFn);
if (!handleAssignments(MIRBuilder, InArgs, Handler))
if (!handleAssignments(MIRBuilder, InArgs, Handler, Info.CallConv,
Info.IsVarArg))
return false;
}

12
llvm/lib/Target/ARM/ARMCallLowering.cpp
View File

@ -259,7 +259,8 @@ bool ARMCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,
ARMOutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret,
AssignFn);
return handleAssignments(MIRBuilder, SplitRetInfos, RetHandler);
return handleAssignments(MIRBuilder, SplitRetInfos, RetHandler,
F.getCallingConv(), F.isVarArg());
}
bool ARMCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
@ -458,7 +459,8 @@ bool ARMCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
if (!MBB.empty())
MIRBuilder.setInstr(*MBB.begin());
if (!handleAssignments(MIRBuilder, SplitArgInfos, ArgHandler))
if (!handleAssignments(MIRBuilder, SplitArgInfos, ArgHandler,
F.getCallingConv(), F.isVarArg()))
return false;
// Move back to the end of the basic block.
@ -551,7 +553,8 @@ bool ARMCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &
auto ArgAssignFn = TLI.CCAssignFnForCall(Info.CallConv, Info.IsVarArg);
ARMOutgoingValueHandler ArgHandler(MIRBuilder, MRI, MIB, ArgAssignFn);
if (!handleAssignments(MIRBuilder, ArgInfos, ArgHandler))
if (!handleAssignments(MIRBuilder, ArgInfos, ArgHandler, Info.CallConv,
Info.IsVarArg))
return false;
// Now we can add the actual call instruction to the correct basic block.
@ -565,7 +568,8 @@ bool ARMCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &
splitToValueTypes(Info.OrigRet, ArgInfos, MF);
auto RetAssignFn = TLI.CCAssignFnForReturn(Info.CallConv, Info.IsVarArg);
CallReturnHandler RetHandler(MIRBuilder, MRI, MIB, RetAssignFn);
if (!handleAssignments(MIRBuilder, ArgInfos, RetHandler))
if (!handleAssignments(MIRBuilder, ArgInfos, RetHandler, Info.CallConv,
Info.IsVarArg))
return false;
}

12
llvm/lib/Target/X86/X86CallLowering.cpp
View File

@ -216,7 +216,8 @@ bool X86CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
}
X86OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, RetCC_X86);
if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
if (!handleAssignments(MIRBuilder, SplitArgs, Handler, F.getCallingConv(),
F.isVarArg()))
return false;
}
@ -364,7 +365,8 @@ bool X86CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
MIRBuilder.setInstr(*MBB.begin());
FormalArgHandler Handler(MIRBuilder, MRI, CC_X86);
if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
if (!handleAssignments(MIRBuilder, SplitArgs, Handler, F.getCallingConv(),
F.isVarArg()))
return false;
// Move back to the end of the basic block.
@ -420,7 +422,8 @@ bool X86CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
}
// Do the actual argument marshalling.
X86OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, CC_X86);
if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
if (!handleAssignments(MIRBuilder, SplitArgs, Handler, Info.CallConv,
Info.IsVarArg))
return false;
bool IsFixed = Info.OrigArgs.empty() ? true : Info.OrigArgs.back().IsFixed;
@ -469,7 +472,8 @@ bool X86CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
return false;
CallReturnHandler Handler(MIRBuilder, MRI, RetCC_X86, MIB);
if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
if (!handleAssignments(MIRBuilder, SplitArgs, Handler, Info.CallConv,
Info.IsVarArg))
return false;
if (!NewRegs.empty())