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[RISCV][test] Add a new test of addition 

Reviewed by: craig.topper

Differential Revision: https://reviews.llvm.org/D100767
This commit is contained in:
Ben Shi 2021-04-20 12:11:56 +08:00
parent 680f3d6de7
commit b7249bf3b5
1 changed files with 17 additions and 0 deletions
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17
llvm/test/CodeGen/RISCV/add-imm.ll
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@ -150,6 +150,23 @@ define i32 @add32_accept(i32 %a) nounwind {
ret i32 %1 ret i32 %1
} }
define signext i32 @add32_sext_accept(i32 signext %a) nounwind {
; RV32I-LABEL: add32_sext_accept:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a0, a0, 1500
; RV32I-NEXT: addi a0, a0, 1499
; RV32I-NEXT: ret
;
; RV64I-LABEL: add32_sext_accept:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, -1097
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: ret
%1 = add i32 %a, 2999
ret i32 %1
}
define i64 @add64_accept(i64 %a) nounwind { define i64 @add64_accept(i64 %a) nounwind {
; RV32I-LABEL: add64_accept: ; RV32I-LABEL: add64_accept:
; RV32I: # %bb.0: ; RV32I: # %bb.0: