forked from OSchip/llvm-project
MC/X86: Rename alternate spellings of ADD{8,16,32} and mark as "code gen only" so they don't get selected by the asm matcher.
llvm-svn: 98098
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@ -2647,6 +2647,17 @@ def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
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} // end isConvertibleToThreeAddress
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} // end isCommutable
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// These are alternate spellings for use by the disassembler, we mark them as
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// code gen only to ensure they aren't matched by the assembler.
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let isCodeGenOnly = 1 in {
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def ADD8rr_alt: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
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"add{b}\t{$src2, $dst|$dst, $src2}", []>;
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def ADD16rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
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"add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
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def ADD32rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
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"add{l}\t{$src2, $dst|$dst, $src2}", []>;
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}
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// Register-Memory Addition
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def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
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(ins GR8 :$src1, i8mem :$src2),
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@ -2664,15 +2675,6 @@ def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
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[(set GR32:$dst, (add GR32:$src1, (load addr:$src2))),
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(implicit EFLAGS)]>;
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// Register-Register Addition - Equivalent to the normal rr forms (ADD8rr,
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// ADD16rr, and ADD32rr), but differently encoded.
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def ADD8mrmrr: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
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"add{b}\t{$src2, $dst|$dst, $src2}", []>;
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def ADD16mrmrr: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
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"add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
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def ADD32mrmrr: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
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"add{l}\t{$src2, $dst|$dst, $src2}", []>;
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// Register-Integer Addition
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def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
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"add{b}\t{$src2, $dst|$dst, $src2}",
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@ -44,3 +44,6 @@ rdtscp
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// CHECK: cmpl %eax, %ebx # encoding: [0x39,0xc3]
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cmpl %eax, %ebx
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// CHECK: addw %ax, %ax # encoding: [0x66,0x01,0xc0]
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addw %ax, %ax
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