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AMDGPU/GlobalISel: Fix selecting llvm.amdgcn.s.getreg 

This introduces the same bug llvm.amdgcn.s.setreg has where if the
user specified an immediate outside of the valid 16-bit range, it will
select into a verifier error.
This commit is contained in:
Matt Arsenault 2020-07-25 12:34:59 -04:00
parent 706d992ced
commit b6ebc77326
3 changed files with 15 additions and 14 deletions
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6
llvm/lib/Target/AMDGPU/SIInstrInfo.td
View File

@ -1389,9 +1389,9 @@ def HWREG {
}
class getHwRegImm<int Reg, int Offset = 0, int Size = 32> {
int ret = !or(Reg,
!or(!shl(Offset, 6),
!shl(!add(Size, -1), 11)));
int ret = !and(!or(Reg,
!or(!shl(Offset, 6),
!shl(!add(Size, -1), 11))), 65535);
}
//===----------------------------------------------------------------------===//

16
llvm/lib/Target/AMDGPU/SOPInstructions.td
View File

@ -806,15 +806,19 @@ let hasSideEffects = 1 in {
let mayLoad = 1 in {
// s_getreg_b32 should use hasSideEffects = 1 for tablegen to allow
// its use in the readcyclecounter selection.
// FIXME: Need to truncate immediate to 16-bits.
def S_GETREG_B32 : SOPK_Pseudo <
"s_getreg_b32",
(outs SReg_32:$sdst), (ins hwreg:$simm16),
"$sdst, $simm16"
>;
"$sdst, $simm16",
[(set i32:$sdst, (int_amdgcn_s_getreg (i32 timm:$simm16)))]> {
let SOPKZext = 1;
}
}
let mayLoad = 0, mayStore =0 in {
// FIXME: Need to truncate immediate to 16-bits.
def S_SETREG_B32 : SOPK_Pseudo <
"s_setreg_b32",
(outs), (ins SReg_32:$sdst, hwreg:$simm16),
@ -1250,14 +1254,6 @@ let SubtargetPredicate = isGFX10Plus in {
SOPP<0x028, (ins s16imm:$simm16), "s_ttracedata_imm $simm16">;
} // End SubtargetPredicate = isGFX10Plus
//===----------------------------------------------------------------------===//
// S_GETREG_B32 Intrinsic Pattern.
//===----------------------------------------------------------------------===//
def : GCNPat <
(int_amdgcn_s_getreg timm:$simm16),
(S_GETREG_B32 (as_i16imm $simm16))
>;
//===----------------------------------------------------------------------===//
// SOP1 Patterns
//===----------------------------------------------------------------------===//

7
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.getreg.ll
View File

@ -2,6 +2,11 @@
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -global-isel -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}s_getreg_test:
; GCN: s_getreg_b32 s{{[0-9]+}}, hwreg(HW_REG_LDS_ALLOC, 8, 23)
define amdgpu_kernel void @s_getreg_test(i32 addrspace(1)* %out) { ; simm16=45574 for lds size.
@ -21,7 +26,7 @@ define amdgpu_kernel void @readnone_s_getreg_test(i32 addrspace(1)* %out) { ; si
ret void
}
declare i32 @llvm.amdgcn.s.getreg(i32) #0
declare i32 @llvm.amdgcn.s.getreg(i32 immarg) #0
attributes #0 = { nounwind readonly }
attributes #1 = { nounwind readnone }