maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[TargetLowering] SimplifyDemandedBits - Merge SIGN_EXTEND+SIGN_EXTEND_VECTOR_INREG handling 

Other than adding consistent demanded elts handling which was a trivial addition, the other differences in functionality will be added in later patches.

llvm-svn: 363710
This commit is contained in:
Simon Pilgrim 2019-06-18 17:57:53 +00:00
parent d4a1c3bb5a
commit b6e7108dcd
1 changed files with 17 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

42
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -1412,49 +1412,41 @@ bool TargetLowering::SimplifyDemandedBits(
Known = Known.zext(BitWidth, true /* ExtendedBitsAreKnownZero */); Known = Known.zext(BitWidth, true /* ExtendedBitsAreKnownZero */);
break; break;
} }
case ISD::SIGN_EXTEND: { case ISD::SIGN_EXTEND:
case ISD::SIGN_EXTEND_VECTOR_INREG: {
SDValue Src = Op.getOperand(0); SDValue Src = Op.getOperand(0);
unsigned InBits = Src.getScalarValueSizeInBits(); EVT SrcVT = Src.getValueType();
unsigned InBits = SrcVT.getScalarSizeInBits();
unsigned InElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1;
bool IsVecInReg = Op.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG;
// If none of the top bits are demanded, convert this into an any_extend. // If none of the top bits are demanded, convert this into an any_extend.
if (DemandedBits.getActiveBits() <= InBits) // TODO: Add SIGN_EXTEND_VECTOR_INREG - ANY_EXTEND_VECTOR_INREG fold.
if (DemandedBits.getActiveBits() <= InBits && !IsVecInReg)
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT, Src)); return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT, Src));
APInt InDemandedBits = DemandedBits.trunc(InBits);
APInt InDemandedElts = DemandedElts.zextOrSelf(InElts);
// Since some of the sign extended bits are demanded, we know that the sign // Since some of the sign extended bits are demanded, we know that the sign
// bit is demanded. // bit is demanded.
APInt InDemandedBits = DemandedBits.trunc(InBits);
InDemandedBits.setBit(InBits - 1); InDemandedBits.setBit(InBits - 1);
if (SimplifyDemandedBits(Src, InDemandedBits, Known, TLO, Depth + 1)) if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO,
Depth + 1))
return true; return true;
assert(!Known.hasConflict() && "Bits known to be one AND zero?"); assert(!Known.hasConflict() && "Bits known to be one AND zero?");
assert(Known.getBitWidth() == InBits && "Src width has changed?");
// If the sign bit is known one, the top bits match. // If the sign bit is known one, the top bits match.
Known = Known.sext(BitWidth); Known = Known.sext(BitWidth);
// If the sign bit is known zero, convert this to a zero extend. // If the sign bit is known zero, convert this to a zero extend.
if (Known.isNonNegative()) // TODO: Add SIGN_EXTEND_VECTOR_INREG - ZERO_EXTEND_VECTOR_INREG fold.
if (Known.isNonNegative() && !IsVecInReg)
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Src)); return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Src));
break; break;
} }
case ISD::SIGN_EXTEND_VECTOR_INREG: {
// TODO - merge this with SIGN_EXTEND above?
SDValue Src = Op.getOperand(0);
unsigned InBits = Src.getScalarValueSizeInBits();
APInt InDemandedBits = DemandedBits.trunc(InBits);
// If some of the sign extended bits are demanded, we know that the sign
// bit is demanded.
if (InBits < DemandedBits.getActiveBits())
InDemandedBits.setBit(InBits - 1);
if (SimplifyDemandedBits(Src, InDemandedBits, Known, TLO, Depth + 1))
return true;
assert(!Known.hasConflict() && "Bits known to be one AND zero?");
// If the sign bit is known one, the top bits match.
Known = Known.sext(BitWidth);
break;
}
case ISD::ANY_EXTEND: { case ISD::ANY_EXTEND: {
SDValue Src = Op.getOperand(0); SDValue Src = Op.getOperand(0);
unsigned InBits = Src.getScalarValueSizeInBits(); unsigned InBits = Src.getScalarValueSizeInBits();