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AMDGPU: Fix verifier error when spilling SGPRs 

The current SGPR spilling test does not stress this
because it is using s_buffer_load instructions to
increase SGPR pressure and spill, but their output
operands have the same SReg_32_XM0 constraint. This fixes
an error when the SReg_32 output from most instructions
is spilled.

llvm-svn: 270301
This commit is contained in:
Matt Arsenault 2016-05-21 00:53:42 +00:00
parent 8f5e008534
commit b6e1cc2a92
2 changed files with 15 additions and 2 deletions
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13
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
View File

@ -584,6 +584,12 @@ void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
if (RI.isSGPRClass(RC)) { if (RI.isSGPRClass(RC)) {
MFI->setHasSpilledSGPRs(); MFI->setHasSpilledSGPRs();
if (TargetRegisterInfo::isVirtualRegister(SrcReg) && RC->getSize() == 4) {
// m0 may not be allowed for readlane.
MachineRegisterInfo &MRI = MF->getRegInfo();
MRI.constrainRegClass(SrcReg, &AMDGPU::SReg_32_XM0RegClass);
}
// We are only allowed to create one new instruction when spilling // We are only allowed to create one new instruction when spilling
// registers, so we need to use pseudo instruction for spilling // registers, so we need to use pseudo instruction for spilling
// SGPRs. // SGPRs.
@ -677,6 +683,13 @@ void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
// FIXME: Maybe this should not include a memoperand because it will be // FIXME: Maybe this should not include a memoperand because it will be
// lowered to non-memory instructions. // lowered to non-memory instructions.
unsigned Opcode = getSGPRSpillRestoreOpcode(RC->getSize()); unsigned Opcode = getSGPRSpillRestoreOpcode(RC->getSize());
if (TargetRegisterInfo::isVirtualRegister(DestReg) && RC->getSize() == 4) {
// m0 may not be allowed for readlane.
MachineRegisterInfo &MRI = MF->getRegInfo();
MRI.constrainRegClass(DestReg, &AMDGPU::SReg_32_XM0RegClass);
}
BuildMI(MBB, MI, DL, get(Opcode), DestReg) BuildMI(MBB, MI, DL, get(Opcode), DestReg)
.addFrameIndex(FrameIndex) // frame_idx .addFrameIndex(FrameIndex) // frame_idx
.addMemOperand(MMO); .addMemOperand(MMO);

4
llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll
View File

@ -1,5 +1,5 @@
; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck %s ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
; These tests check that the compiler won't crash when it needs to spill ; These tests check that the compiler won't crash when it needs to spill
; SGPRs. ; SGPRs.