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[AArch64,Assembler] Compiler support for ID_MMFR5_EL1 

Summary: Add read-only system register ID_MMFR5_EL1 and unit tests.

Subscribers: kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69039

llvm-svn: 375010
This commit is contained in:
Mark Murray 2019-10-16 15:59:06 +00:00
parent fe2d15b39b
commit b6dd128621
4 changed files with 9 additions and 0 deletions
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1
llvm/lib/Target/AArch64/AArch64SystemOperands.td
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@ -612,6 +612,7 @@ def : ROSysReg<"ISR_EL1", 0b11, 0b000, 0b1100, 0b0001, 0b000>;
def : ROSysReg<"CNTPCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b001>;
def : ROSysReg<"CNTVCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b010>;
def : ROSysReg<"ID_MMFR4_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b110>;
def : ROSysReg<"ID_MMFR5_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b110>;
// Trace registers
// Op0 Op1 CRn CRm Op2

4
llvm/test/MC/AArch64/basic-a64-diagnostics.s
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@ -3581,6 +3581,7 @@
msr ID_MMFR2_EL1, x12
msr ID_MMFR3_EL1, x12
msr ID_MMFR4_EL1, x12
msr ID_MMFR5_EL1, x12
msr ID_ISAR0_EL1, x12
msr ID_ISAR1_EL1, x12
msr ID_ISAR2_EL1, x12
@ -3680,6 +3681,9 @@
// CHECK-ERROR-NEXT: msr ID_MMFR4_EL1, x12
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr ID_MMFR5_EL1, x12
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr ID_ISAR0_EL1, x12
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate

2
llvm/test/MC/AArch64/basic-a64-instructions.s
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@ -4295,6 +4295,7 @@ _func:
mrs x9, ID_MMFR2_EL1
mrs x9, ID_MMFR3_EL1
mrs x9, ID_MMFR4_EL1
mrs x9, ID_MMFR5_EL1
mrs x9, ID_ISAR0_EL1
mrs x9, ID_ISAR1_EL1
mrs x9, ID_ISAR2_EL1
@ -4596,6 +4597,7 @@ _func:
// CHECK: mrs x9, {{id_mmfr2_el1|ID_MMFR2_EL1}} // encoding: [0xc9,0x01,0x38,0xd5]
// CHECK: mrs x9, {{id_mmfr3_el1|ID_MMFR3_EL1}} // encoding: [0xe9,0x01,0x38,0xd5]
// CHECK: mrs x9, {{id_mmfr4_el1|ID_MMFR4_EL1}} // encoding: [0xc9,0x02,0x38,0xd5]
// CHECK: mrs x9, {{id_mmfr5_el1|ID_MMFR5_EL1}} // encoding: [0xc9,0x03,0x38,0xd5]
// CHECK: mrs x9, {{id_isar0_el1|ID_ISAR0_EL1}} // encoding: [0x09,0x02,0x38,0xd5]
// CHECK: mrs x9, {{id_isar1_el1|ID_ISAR1_EL1}} // encoding: [0x29,0x02,0x38,0xd5]
// CHECK: mrs x9, {{id_isar2_el1|ID_ISAR2_EL1}} // encoding: [0x49,0x02,0x38,0xd5]

2
llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
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@ -3513,6 +3513,7 @@
# CHECK: mrs x9, {{id_mmfr2_el1|ID_MMFR2_EL1}}
# CHECK: mrs x9, {{id_mmfr3_el1|ID_MMFR3_EL1}}
# CHECK: mrs x9, {{id_mmfr4_el1|ID_MMFR4_EL1}}
# CHECK: mrs x9, {{id_mmfr5_el1|ID_MMFR5_EL1}}
# CHECK: mrs x9, {{id_isar0_el1|ID_ISAR0_EL1}}
# CHECK: mrs x9, {{id_isar1_el1|ID_ISAR1_EL1}}
# CHECK: mrs x9, {{id_isar2_el1|ID_ISAR2_EL1}}
@ -4069,6 +4070,7 @@
0xc9 0x1 0x38 0xd5
0xe9 0x1 0x38 0xd5
0xc9 0x2 0x38 0xd5
0xc9 0x3 0x38 0xd5
0x9 0x2 0x38 0xd5
0x29 0x2 0x38 0xd5
0x49 0x2 0x38 0xd5