forked from OSchip/llvm-project
[PowerPC] Extend custom lower of vector truncate to handle wider input
Current custom lowering of truncate vector handles a source of up to 128 bits, but that only uses one of the two shuffle vector operands. Extend it to use both operands to handle 256 bit sources. Differential Revision: https://reviews.llvm.org/D68035
This commit is contained in:
Roland Froese
parent
1f6c4d829c
commit
b6d7ed469f
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@ -7862,20 +7862,45 @@ SDValue PPCTargetLowering::LowerTRUNCATEVector(SDValue Op,
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// <uu, uu, uu, uu, uu, uu, LSB2|MSB2, LSB1|MSB1> to
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// <u, u, u, u, u, u, u, u, u, u, u, u, u, u, LSB2, LSB1>
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assert(Op.getValueType().isVector() && "Vector type expected.");
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SDLoc DL(Op);
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SDValue N1 = Op.getOperand(0);
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unsigned SrcSize = N1.getValueType().getSizeInBits();
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assert(SrcSize <= 128 && "Source must fit in an Altivec/VSX vector");
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SDValue WideSrc = SrcSize == 128 ? N1 : widenVec(DAG, N1, DL);
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EVT TrgVT = Op.getValueType();
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assert(TrgVT.isVector() && "Vector type expected.");
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unsigned TrgNumElts = TrgVT.getVectorNumElements();
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EVT EltVT = TrgVT.getVectorElementType();
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if (!isOperationCustom(Op.getOpcode(), TrgVT) ||
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TrgVT.getSizeInBits() > 128 || !isPowerOf2_32(TrgNumElts) ||
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!isPowerOf2_32(EltVT.getSizeInBits()))
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return SDValue();
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SDValue N1 = Op.getOperand(0);
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EVT SrcVT = N1.getValueType();
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unsigned SrcSize = SrcVT.getSizeInBits();
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if (SrcSize > 256 ||
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!isPowerOf2_32(SrcVT.getVectorNumElements()) ||
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!isPowerOf2_32(SrcVT.getVectorElementType().getSizeInBits()))
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return SDValue();
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if (SrcSize == 256 && SrcVT.getVectorNumElements() < 2)
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return SDValue();
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unsigned WideNumElts = 128 / EltVT.getSizeInBits();
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EVT WideVT = EVT::getVectorVT(*DAG.getContext(), EltVT, WideNumElts);
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SDLoc DL(Op);
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SDValue Op1, Op2;
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if (SrcSize == 256) {
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EVT VecIdxTy = getVectorIdxTy(DAG.getDataLayout());
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EVT SplitVT =
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N1.getValueType().getHalfNumVectorElementsVT(*DAG.getContext());
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unsigned SplitNumElts = SplitVT.getVectorNumElements();
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Op1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, N1,
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DAG.getConstant(0, DL, VecIdxTy));
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Op2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, N1,
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DAG.getConstant(SplitNumElts, DL, VecIdxTy));
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}
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else {
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Op1 = SrcSize == 128 ? N1 : widenVec(DAG, N1, DL);
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Op2 = DAG.getUNDEF(WideVT);
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}
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// First list the elements we want to keep.
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unsigned SizeMult = SrcSize / TrgVT.getSizeInBits();
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SmallVector<int, 16> ShuffV;
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@ -7891,8 +7916,9 @@ SDValue PPCTargetLowering::LowerTRUNCATEVector(SDValue Op,
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// ShuffV.push_back(i + WideNumElts);
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ShuffV.push_back(WideNumElts + 1);
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SDValue Conv = DAG.getNode(ISD::BITCAST, DL, WideVT, WideSrc);
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return DAG.getVectorShuffle(WideVT, DL, Conv, DAG.getUNDEF(WideVT), ShuffV);
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Op1 = DAG.getNode(ISD::BITCAST, DL, WideVT, Op1);
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Op2 = DAG.getNode(ISD::BITCAST, DL, WideVT, Op2);
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return DAG.getVectorShuffle(WideVT, DL, Op1, Op2, ShuffV);
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}
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/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
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@ -10750,13 +10776,11 @@ void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
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Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
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return;
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case ISD::TRUNCATE: {
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EVT TrgVT = N->getValueType(0);
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EVT OpVT = N->getOperand(0).getValueType();
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if (TrgVT.isVector() &&
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isOperationCustom(N->getOpcode(), TrgVT) &&
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OpVT.getSizeInBits() <= 128 &&
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isPowerOf2_32(OpVT.getVectorElementType().getSizeInBits()))
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Results.push_back(LowerTRUNCATEVector(SDValue(N, 0), DAG));
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if (!N->getValueType(0).isVector())
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return;
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SDValue Lowered = LowerTRUNCATEVector(SDValue(N, 0), DAG);
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if (Lowered)
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Results.push_back(Lowered);
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return;
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}
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case ISD::BITCAST:
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@ -0,0 +1,189 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mattr=+vsx -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mattr=+vsx -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s --check-prefix=CHECK-BE
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define dso_local <8 x i8> @test8x32(i32 %i1, i32 %i2, i32 %i3, i32 %i4,
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i32 %i5, i32 %i6, i32 %i7, i32 %i8) {
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; CHECK-LABEL: test8x32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: rldimi r3, r4, 32, 0
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; CHECK-NEXT: rldimi r5, r6, 32, 0
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; CHECK-NEXT: addis r11, r2, .LCPI0_0@toc@ha
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; CHECK-NEXT: rldimi r7, r8, 32, 0
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; CHECK-NEXT: rldimi r9, r10, 32, 0
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; CHECK-NEXT: mtfprd f0, r3
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; CHECK-NEXT: addi r3, r11, .LCPI0_0@toc@l
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; CHECK-NEXT: mtfprd f1, r5
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; CHECK-NEXT: lvx v4, 0, r3
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; CHECK-NEXT: mtfprd f2, r7
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; CHECK-NEXT: mtfprd f3, r9
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; CHECK-NEXT: xxmrghd v2, vs1, vs0
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; CHECK-NEXT: xxmrghd v3, vs3, vs2
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; CHECK-NEXT: vperm v2, v3, v2, v4
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: test8x32:
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; CHECK-BE: # %bb.0:
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; CHECK-BE-NEXT: stw r10, -80(r1)
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; CHECK-BE-NEXT: stw r9, -96(r1)
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; CHECK-BE-NEXT: stw r8, -112(r1)
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; CHECK-BE-NEXT: stw r7, -128(r1)
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; CHECK-BE-NEXT: stw r6, -16(r1)
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; CHECK-BE-NEXT: stw r5, -32(r1)
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; CHECK-BE-NEXT: stw r4, -48(r1)
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; CHECK-BE-NEXT: stw r3, -64(r1)
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; CHECK-BE-NEXT: addi r3, r1, -80
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; CHECK-BE-NEXT: lxvw4x v2, 0, r3
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; CHECK-BE-NEXT: addi r3, r1, -96
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; CHECK-BE-NEXT: lxvw4x v3, 0, r3
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; CHECK-BE-NEXT: addi r3, r1, -112
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; CHECK-BE-NEXT: lxvw4x v4, 0, r3
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; CHECK-BE-NEXT: addi r3, r1, -128
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; CHECK-BE-NEXT: lxvw4x v5, 0, r3
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; CHECK-BE-NEXT: addi r3, r1, -16
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; CHECK-BE-NEXT: lxvw4x v0, 0, r3
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; CHECK-BE-NEXT: addi r3, r1, -32
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; CHECK-BE-NEXT: lxvw4x v1, 0, r3
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; CHECK-BE-NEXT: addi r3, r1, -48
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; CHECK-BE-NEXT: lxvw4x v6, 0, r3
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; CHECK-BE-NEXT: addi r3, r1, -64
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; CHECK-BE-NEXT: lxvw4x v7, 0, r3
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; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha
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; CHECK-BE-NEXT: vmrghw v2, v3, v2
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; CHECK-BE-NEXT: vmrghw v3, v5, v4
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; CHECK-BE-NEXT: vmrghw v4, v1, v0
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; CHECK-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l
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; CHECK-BE-NEXT: xxmrghd v2, v3, v2
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; CHECK-BE-NEXT: lxvw4x v8, 0, r3
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; CHECK-BE-NEXT: vmrghw v5, v7, v6
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; CHECK-BE-NEXT: xxmrghd v3, v5, v4
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; CHECK-BE-NEXT: vperm v2, v3, v2, v8
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; CHECK-BE-NEXT: blr
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%v10 = insertelement <8 x i32> undef, i32 %i1, i32 0
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%v11 = insertelement <8 x i32> %v10, i32 %i2, i32 1
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%v12 = insertelement <8 x i32> %v11, i32 %i3, i32 2
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%v13 = insertelement <8 x i32> %v12, i32 %i4, i32 3
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%v14 = insertelement <8 x i32> %v13, i32 %i5, i32 4
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%v15 = insertelement <8 x i32> %v14, i32 %i6, i32 5
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%v16 = insertelement <8 x i32> %v15, i32 %i7, i32 6
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%v17 = insertelement <8 x i32> %v16, i32 %i8, i32 7
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%v2 = trunc <8 x i32> %v17 to <8 x i8>
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ret <8 x i8> %v2
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}
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define dso_local <4 x i16> @test4x64(i64 %i1, i64 %i2, i64 %i3, i64 %i4) {
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; CHECK-LABEL: test4x64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addis r7, r2, .LCPI1_0@toc@ha
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; CHECK-NEXT: mtfprd f0, r5
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; CHECK-NEXT: mtfprd f1, r6
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; CHECK-NEXT: mtfprd f2, r3
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; CHECK-NEXT: addi r3, r7, .LCPI1_0@toc@l
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; CHECK-NEXT: mtfprd f3, r4
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; CHECK-NEXT: xxmrghd v2, vs1, vs0
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; CHECK-NEXT: lvx v4, 0, r3
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; CHECK-NEXT: xxmrghd v3, vs3, vs2
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; CHECK-NEXT: vperm v2, v2, v3, v4
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: test4x64:
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; CHECK-BE: # %bb.0:
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; CHECK-BE-NEXT: std r6, -8(r1)
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; CHECK-BE-NEXT: std r5, -16(r1)
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; CHECK-BE-NEXT: std r4, -24(r1)
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; CHECK-BE-NEXT: std r3, -32(r1)
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; CHECK-BE-NEXT: addi r3, r1, -32
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; CHECK-BE-NEXT: addis r4, r2, .LCPI1_0@toc@ha
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; CHECK-BE-NEXT: addi r7, r1, -16
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; CHECK-BE-NEXT: lxvd2x v3, 0, r3
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; CHECK-BE-NEXT: addi r3, r4, .LCPI1_0@toc@l
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; CHECK-BE-NEXT: lxvd2x v2, 0, r7
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; CHECK-BE-NEXT: lxvw4x v4, 0, r3
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; CHECK-BE-NEXT: vperm v2, v3, v2, v4
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; CHECK-BE-NEXT: blr
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%v10 = insertelement <4 x i64> undef, i64 %i1, i32 0
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%v11 = insertelement <4 x i64> %v10, i64 %i2, i32 1
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%v12 = insertelement <4 x i64> %v11, i64 %i3, i32 2
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%v13 = insertelement <4 x i64> %v12, i64 %i4, i32 3
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%v2 = trunc <4 x i64> %v13 to <4 x i16>
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ret <4 x i16> %v2
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}
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define dso_local <8 x i16> @test8x24(i32 %i1, i32 %i2, i32 %i3, i32 %i4,
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i32 %i5, i32 %i6, i32 %i7, i32 %i8) {
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; CHECK-LABEL: test8x24:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mtvsrd v2, r3
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; CHECK-NEXT: mtvsrd v3, r4
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; CHECK-NEXT: mtvsrd v4, r5
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; CHECK-NEXT: mtvsrd v5, r6
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; CHECK-NEXT: mtvsrd v0, r7
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; CHECK-NEXT: mtvsrd v1, r8
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; CHECK-NEXT: vmrghh v2, v3, v2
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; CHECK-NEXT: mtvsrd v3, r9
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; CHECK-NEXT: vmrghh v4, v5, v4
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; CHECK-NEXT: mtvsrd v5, r10
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; CHECK-NEXT: vmrghh v0, v1, v0
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; CHECK-NEXT: vmrghh v3, v5, v3
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; CHECK-NEXT: vmrglw v2, v4, v2
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; CHECK-NEXT: vmrglw v3, v3, v0
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; CHECK-NEXT: xxmrgld v2, v3, v2
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: test8x24:
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; CHECK-BE: # %bb.0:
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; CHECK-BE-NEXT: sth r10, -16(r1)
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; CHECK-BE-NEXT: sth r9, -32(r1)
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; CHECK-BE-NEXT: sth r8, -48(r1)
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; CHECK-BE-NEXT: sth r7, -64(r1)
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; CHECK-BE-NEXT: sth r6, -80(r1)
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; CHECK-BE-NEXT: sth r5, -96(r1)
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; CHECK-BE-NEXT: sth r4, -112(r1)
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; CHECK-BE-NEXT: sth r3, -128(r1)
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; CHECK-BE-NEXT: addi r3, r1, -16
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; CHECK-BE-NEXT: lxvw4x v2, 0, r3
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; CHECK-BE-NEXT: addi r3, r1, -32
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; CHECK-BE-NEXT: lxvw4x v3, 0, r3
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; CHECK-BE-NEXT: addi r3, r1, -48
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; CHECK-BE-NEXT: lxvw4x v4, 0, r3
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; CHECK-BE-NEXT: addi r3, r1, -64
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; CHECK-BE-NEXT: lxvw4x v5, 0, r3
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; CHECK-BE-NEXT: addi r3, r1, -80
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; CHECK-BE-NEXT: lxvw4x v0, 0, r3
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; CHECK-BE-NEXT: addi r3, r1, -96
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; CHECK-BE-NEXT: lxvw4x v1, 0, r3
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; CHECK-BE-NEXT: addi r3, r1, -112
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; CHECK-BE-NEXT: lxvw4x v6, 0, r3
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; CHECK-BE-NEXT: addi r3, r1, -128
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; CHECK-BE-NEXT: lxvw4x v7, 0, r3
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; CHECK-BE-NEXT: vmrghh v2, v3, v2
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; CHECK-BE-NEXT: vmrghh v3, v5, v4
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; CHECK-BE-NEXT: vmrghh v4, v1, v0
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; CHECK-BE-NEXT: vmrghw v2, v3, v2
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; CHECK-BE-NEXT: vmrghh v5, v7, v6
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; CHECK-BE-NEXT: vmrghw v3, v5, v4
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; CHECK-BE-NEXT: xxmrghd v2, v3, v2
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; CHECK-BE-NEXT: blr
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%i11 = trunc i32 %i1 to i24
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%i21 = trunc i32 %i2 to i24
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%i31 = trunc i32 %i3 to i24
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%i41 = trunc i32 %i4 to i24
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%i51 = trunc i32 %i5 to i24
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%i61 = trunc i32 %i6 to i24
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%i71 = trunc i32 %i7 to i24
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%i81 = trunc i32 %i8 to i24
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%v10 = insertelement <8 x i24> undef, i24 %i11, i32 0
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%v11 = insertelement <8 x i24> %v10, i24 %i21, i32 1
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%v12 = insertelement <8 x i24> %v11, i24 %i31, i32 2
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%v13 = insertelement <8 x i24> %v12, i24 %i41, i32 3
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%v14 = insertelement <8 x i24> %v13, i24 %i51, i32 4
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%v15 = insertelement <8 x i24> %v14, i24 %i61, i32 5
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%v16 = insertelement <8 x i24> %v15, i24 %i71, i32 6
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%v17 = insertelement <8 x i24> %v16, i24 %i81, i32 7
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%v2 = trunc <8 x i24> %v17 to <8 x i16>
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ret <8 x i16> %v2
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}
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