forked from OSchip/llvm-project
ARM sched model: Add more ALU and CMP instructions
llvm-svn: 183258
This commit is contained in:
Arnold Schwaighofer
parent
d5b9794a53
commit
b6843f17eb
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@ -1327,7 +1327,7 @@ class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
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: AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
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IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
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[(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
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Requires<[IsARM, HasV6]> {
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Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
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bits<4> Rd;
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bits<4> Rm;
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bits<2> rot;
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@ -1340,11 +1340,11 @@ class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
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class AI_ext_rrot_np<bits<8> opcod, string opc>
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: AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
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IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
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Requires<[IsARM, HasV6]> {
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Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
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bits<2> rot;
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let Inst{19-16} = 0b1111;
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let Inst{11-10} = rot;
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}
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}
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/// AI_exta_rrot - A binary operation with two forms: one whose operand is a
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/// register and one whose operand is a register rotated by 8/16/24.
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@ -1353,7 +1353,7 @@ class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
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IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
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[(set GPRnopc:$Rd, (opnode GPR:$Rn,
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(rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
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Requires<[IsARM, HasV6]> {
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Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
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bits<4> Rd;
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bits<4> Rm;
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bits<4> Rn;
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@ -1368,7 +1368,7 @@ class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
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class AI_exta_rrot_np<bits<8> opcod, string opc>
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: AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
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IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
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Requires<[IsARM, HasV6]> {
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Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
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bits<4> Rn;
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bits<2> rot;
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let Inst{19-16} = Rn;
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@ -1863,7 +1863,8 @@ def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
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let isNotDuplicable = 1 in {
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def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
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4, IIC_iALUr,
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[(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
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[(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>,
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Sched<[WriteALU, ReadALU]>;
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let AddedComplexity = 10 in {
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def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
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@ -1923,11 +1924,11 @@ def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
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let hasSideEffects = 1 in {
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def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
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4, IIC_iALUi, []>;
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4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
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def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
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(ins i32imm:$label, nohash_imm:$id, pred:$p),
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4, IIC_iALUi, []>;
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4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
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}
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//===----------------------------------------------------------------------===//
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@ -2955,7 +2956,7 @@ defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
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let neverHasSideEffects = 1 in
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def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
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"mov", "\t$Rd, $Rm", []>, UnaryDP {
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"mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
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bits<4> Rd;
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bits<4> Rm;
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@ -2969,7 +2970,7 @@ def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
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// A version for the smaller set of tail call registers.
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let neverHasSideEffects = 1 in
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def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
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IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
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IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
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bits<4> Rd;
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bits<4> Rm;
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@ -2982,7 +2983,8 @@ def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
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def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
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DPSoRegRegFrm, IIC_iMOVsr,
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"mov", "\t$Rd, $src",
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[(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP {
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[(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
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Sched<[WriteALU]> {
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bits<4> Rd;
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bits<12> src;
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let Inst{15-12} = Rd;
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@ -2998,7 +3000,7 @@ def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
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def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
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DPSoRegImmFrm, IIC_iMOVsr,
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"mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
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UnaryDP {
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UnaryDP, Sched<[WriteALU]> {
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bits<4> Rd;
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bits<12> src;
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let Inst{15-12} = Rd;
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@ -3011,7 +3013,8 @@ def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
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let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
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def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
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"mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
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"mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP,
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Sched<[WriteALU]> {
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bits<4> Rd;
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bits<12> imm;
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let Inst{25} = 1;
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@ -3025,7 +3028,7 @@ def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
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DPFrm, IIC_iMOVi,
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"movw", "\t$Rd, $imm",
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[(set GPR:$Rd, imm0_65535:$imm)]>,
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Requires<[IsARM, HasV6T2]>, UnaryDP {
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Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> {
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bits<4> Rd;
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bits<16> imm;
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let Inst{15-12} = Rd;
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@ -3041,7 +3044,8 @@ def : InstAlias<"mov${p} $Rd, $imm",
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Requires<[IsARM]>;
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def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
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(ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
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(ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
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Sched<[WriteALU]>;
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let Constraints = "$src = $Rd" in {
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def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
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@ -3051,7 +3055,7 @@ def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
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[(set GPRnopc:$Rd,
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(or (and GPR:$src, 0xffff),
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lo16AllZero:$imm))]>, UnaryDP,
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Requires<[IsARM, HasV6T2]> {
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Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> {
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bits<4> Rd;
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bits<16> imm;
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let Inst{15-12} = Rd;
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@ -3063,7 +3067,8 @@ def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
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}
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def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
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(ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
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(ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
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Sched<[WriteALU]>;
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} // Constraints
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@ -3073,7 +3078,7 @@ def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
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let Uses = [CPSR] in
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def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
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[(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
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Requires<[IsARM]>;
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Requires<[IsARM]>, Sched<[WriteALU]>;
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// These aren't really mov instructions, but we have to define them this way
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// due to flag operands.
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@ -3081,10 +3086,10 @@ def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
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let Defs = [CPSR] in {
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def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
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[(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
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Requires<[IsARM]>;
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Sched<[WriteALU]>, Requires<[IsARM]>;
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def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
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[(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
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Requires<[IsARM]>;
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Sched<[WriteALU]>, Requires<[IsARM]>;
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}
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//===----------------------------------------------------------------------===//
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@ -3250,7 +3255,8 @@ class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
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list<dag> pattern = [],
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dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
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string asm = "\t$Rd, $Rn, $Rm">
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: AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
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: AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>,
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Sched<[WriteALU, ReadALU, ReadALU]> {
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bits<4> Rn;
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bits<4> Rd;
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bits<4> Rm;
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@ -3326,7 +3332,7 @@ def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
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def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
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MulFrm /* for convenience */, NoItinerary, "usad8",
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"\t$Rd, $Rn, $Rm", []>,
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Requires<[IsARM, HasV6]> {
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Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> {
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bits<4> Rd;
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bits<4> Rn;
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bits<4> Rm;
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@ -3340,7 +3346,7 @@ def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
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def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
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MulFrm /* for convenience */, NoItinerary, "usada8",
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"\t$Rd, $Rn, $Rm, $Ra", []>,
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Requires<[IsARM, HasV6]> {
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Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{
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bits<4> Rd;
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bits<4> Rn;
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bits<4> Rm;
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@ -3473,7 +3479,7 @@ def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
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def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
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"mvn", "\t$Rd, $Rm",
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[(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
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[(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
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bits<4> Rd;
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bits<4> Rm;
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let Inst{25} = 0;
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@ -3484,7 +3490,8 @@ def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
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}
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def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
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DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
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[(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP {
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[(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
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Sched<[WriteALU]> {
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bits<4> Rd;
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bits<12> shift;
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let Inst{25} = 0;
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@ -3496,7 +3503,8 @@ def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
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}
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def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
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DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
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[(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP {
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[(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
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Sched<[WriteALU]> {
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bits<4> Rd;
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bits<12> shift;
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let Inst{25} = 0;
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@ -3511,7 +3519,7 @@ def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
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let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
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def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
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IIC_iMVNi, "mvn", "\t$Rd, $imm",
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[(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
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[(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
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bits<4> Rd;
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bits<12> imm;
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let Inst{25} = 1;
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@ -4022,7 +4030,8 @@ def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
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let isCompare = 1, Defs = [CPSR] in {
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def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iCMPi,
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"cmn", "\t$Rn, $imm",
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[(ARMcmn GPR:$Rn, so_imm:$imm)]> {
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[(ARMcmn GPR:$Rn, so_imm:$imm)]>,
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Sched<[WriteCMP, ReadALU]> {
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bits<4> Rn;
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bits<12> imm;
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let Inst{25} = 1;
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@ -4038,7 +4047,7 @@ def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iCMPi,
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def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
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"cmn", "\t$Rn, $Rm",
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[(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
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GPR:$Rn, GPR:$Rm)]> {
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GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
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bits<4> Rn;
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bits<4> Rm;
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let isCommutable = 1;
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@ -4056,7 +4065,8 @@ def CMNzrsi : AI1<0b1011, (outs),
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(ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
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"cmn", "\t$Rn, $shift",
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[(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
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GPR:$Rn, so_reg_imm:$shift)]> {
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GPR:$Rn, so_reg_imm:$shift)]>,
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Sched<[WriteCMPsi, ReadALU]> {
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bits<4> Rn;
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bits<12> shift;
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let Inst{25} = 0;
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@ -4074,7 +4084,8 @@ def CMNzrsr : AI1<0b1011, (outs),
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(ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
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"cmn", "\t$Rn, $shift",
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[(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
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GPRnopc:$Rn, so_reg_reg:$shift)]> {
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GPRnopc:$Rn, so_reg_reg:$shift)]>,
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Sched<[WriteCMPsr, ReadALU]> {
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bits<4> Rn;
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bits<12> shift;
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let Inst{25} = 0;
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@ -4129,20 +4140,20 @@ let isCommutable = 1, isSelect = 1 in
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def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
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4, IIC_iCMOVr,
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[/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
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RegConstraint<"$false = $Rd">;
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RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
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def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
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(ins GPR:$false, so_reg_imm:$shift, pred:$p),
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4, IIC_iCMOVsr,
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[/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift,
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imm:$cc, CCR:$ccr))*/]>,
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RegConstraint<"$false = $Rd">;
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RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
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def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
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(ins GPR:$false, so_reg_reg:$shift, pred:$p),
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4, IIC_iCMOVsr,
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[/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
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imm:$cc, CCR:$ccr))*/]>,
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RegConstraint<"$false = $Rd">;
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RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
|
||||
|
||||
|
||||
let isMoveImm = 1 in
|
||||
|
|
@ -4150,14 +4161,15 @@ def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
|
|||
(ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
|
||||
4, IIC_iMOVi,
|
||||
[]>,
|
||||
RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
|
||||
RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
|
||||
Sched<[WriteALU]>;
|
||||
|
||||
let isMoveImm = 1 in
|
||||
def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
|
||||
(ins GPR:$false, so_imm:$imm, pred:$p),
|
||||
4, IIC_iCMOVi,
|
||||
[/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
|
||||
RegConstraint<"$false = $Rd">;
|
||||
RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
|
||||
|
||||
// Two instruction predicate mov immediate.
|
||||
let isMoveImm = 1 in
|
||||
|
|
@ -4170,7 +4182,7 @@ def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
|
|||
(ins GPR:$false, so_imm:$imm, pred:$p),
|
||||
4, IIC_iCMOVi,
|
||||
[/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
|
||||
RegConstraint<"$false = $Rd">;
|
||||
RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
|
||||
|
||||
} // neverHasSideEffects
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue