forked from OSchip/llvm-project
The andi16, addiusp and jraddiusp micromips instructions were missing dedicated decoder methods in MipsDisassembler.cpp to properly decode immediate operands. These methods are added together with corresponding tests.
llvm-svn: 223006
This commit is contained in:
parent
a056ac8a98
commit
b682ddf33a
llvm
lib/Target/Mips
test/MC
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@ -340,6 +340,15 @@ static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
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static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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/// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
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/// handle.
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template <typename InsnType>
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@ -1591,6 +1600,36 @@ static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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int32_t DecodedValue;
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switch (Insn) {
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case 0: DecodedValue = 256; break;
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case 1: DecodedValue = 257; break;
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case 510: DecodedValue = -258; break;
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case 511: DecodedValue = -257; break;
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default: DecodedValue = SignExtend32<9>(Insn); break;
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}
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Inst.addOperand(MCOperand::CreateImm(DecodedValue << 2));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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// Insn must be >= 0, since it is unsigned that condition is always true.
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assert(Insn < 16);
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int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
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255, 32768, 65535};
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Inst.addOperand(MCOperand::CreateImm(DecodedValues[Insn]));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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Inst.addOperand(MCOperand::CreateImm(Insn << 2));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeRegListOperand(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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@ -13,6 +13,7 @@ def simm12 : Operand<i32> {
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def uimm5_lsl2 : Operand<OtherVT> {
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let EncoderMethod = "getUImm5Lsl2Encoding";
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let DecoderMethod = "DecodeUImm5lsl2";
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}
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def uimm6_lsl2 : Operand<i32> {
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@ -22,6 +23,7 @@ def uimm6_lsl2 : Operand<i32> {
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def simm9_addiusp : Operand<i32> {
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let EncoderMethod = "getSImm9AddiuspValue";
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let DecoderMethod = "DecodeSimm9SP";
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}
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def uimm3_shift : Operand<i32> {
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@ -35,6 +37,7 @@ def simm3_lsa2 : Operand<i32> {
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def uimm4_andi : Operand<i32> {
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let EncoderMethod = "getUImm4AndValue";
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let DecoderMethod = "DecodeANDI16Imm";
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}
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def immSExtAddiur2 : ImmLeaf<i32, [{return Imm == 1 || Imm == -1 ||
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@ -16,6 +16,21 @@
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# CHECK: addiu $9, $6, -15001
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0x31 0x26 0xc5 0x67
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# CHECK: addiusp -16
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0x4f 0xf9
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# CHECK: addiusp -1028
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0x4f 0xff
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# CHECK: addiusp -1032
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0x4f 0xfd
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# CHECK: addiusp 1024
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0x4c 0x01
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# CHECK: addiusp 1028
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0x4c 0x03
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# CHECK: addu $9, $6, $7
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0x00 0xe6 0x49 0x50
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@ -61,6 +76,9 @@
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# CHECK: andi $9, $6, 17767
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0xd1 0x26 0x45 0x67
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# CHECK: andi16 $16, $2, 31
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0x2c 0x29
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# CHECK: or $3, $4, $5
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0x00 0xa4 0x1a 0x90
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@ -229,6 +247,9 @@
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# CHECK: jr $7
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0x00 0x07 0x0f 0x3c
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# CHECK: jraddiusp 20
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0x47 0x05
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# CHECK: beq $9, $6, 1332
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0x94 0xc9 0x02 0x9a
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@ -16,9 +16,27 @@
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# CHECK: addiu $9, $6, -15001
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0x26 0x31 0x67 0xc5
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# CHECK: addiusp -16
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0xf9 0x4f
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# CHECK: addiusp -1028
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0xff 0x4f
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# CHECK: addiusp -1032
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0xfd 0x4f
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# CHECK: addiusp 1024
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0x01 0x4c
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# CHECK: addiusp 1028
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0x03 0x4c
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# CHECK: addu $9, $6, $7
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0xe6 0x00 0x50 0x49
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# CHECK: andi16 $16, $2, 31
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0x29 0x2c
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# CHECK: sub $9, $6, $7
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0xe6 0x00 0x90 0x49
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@ -229,6 +247,9 @@
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# CHECK: jr $7
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0x07 0x00 0x3c 0x0f
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# CHECK: jraddiusp 20
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0x05 0x47
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# CHECK: beq $9, $6, 1332
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0xc9 0x94 0x9a 0x02
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@ -32,6 +32,10 @@
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# CHECK-EL: addiur2 $6, $7, -1 # encoding: [0x7e,0x6f]
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# CHECK-EL: addiur2 $6, $7, 12 # encoding: [0x76,0x6f]
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# CHECK-EL: addius5 $7, -2 # encoding: [0xfc,0x4c]
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# CHECK-EL: addiusp -1028 # encoding: [0xff,0x4f]
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# CHECK-EL: addiusp -1032 # encoding: [0xfd,0x4f]
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# CHECK-EL: addiusp 1024 # encoding: [0x01,0x4c]
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# CHECK-EL: addiusp 1028 # encoding: [0x03,0x4c]
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# CHECK-EL: addiusp -16 # encoding: [0xf9,0x4f]
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# CHECK-EL: mfhi $9 # encoding: [0x09,0x46]
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# CHECK-EL: mflo $9 # encoding: [0x49,0x46]
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@ -71,6 +75,10 @@
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# CHECK-EB: addiur2 $6, $7, -1 # encoding: [0x6f,0x7e]
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# CHECK-EB: addiur2 $6, $7, 12 # encoding: [0x6f,0x76]
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# CHECK-EB: addius5 $7, -2 # encoding: [0x4c,0xfc]
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# CHECK-EB: addiusp -1028 # encoding: [0x4f,0xff]
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# CHECK-EB: addiusp -1032 # encoding: [0x4f,0xfd]
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# CHECK-EB: addiusp 1024 # encoding: [0x4c,0x01]
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# CHECK-EB: addiusp 1028 # encoding: [0x4c,0x03]
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# CHECK-EB: addiusp -16 # encoding: [0x4f,0xf9]
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# CHECK-EB: mfhi $9 # encoding: [0x46,0x09]
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# CHECK-EB: mflo $9 # encoding: [0x46,0x49]
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@ -108,6 +116,10 @@
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addiur2 $6, $7, -1
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addiur2 $6, $7, 12
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addius5 $7, -2
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addiusp -1028
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addiusp -1032
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addiusp 1024
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addiusp 1028
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addiusp -16
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mfhi $9
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mflo $9
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