forked from OSchip/llvm-project
R600: Use SIGN_EXTEND_INREG for SEXT loads
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Matt Arsenault <Matthew.Arsenault@amd.com> llvm-svn: 238229
This commit is contained in:
Jan Vesely
parent
a2143fa244
commit
b670d37105
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@ -1593,19 +1593,16 @@ SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
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if (LoadNode->getExtensionType() == ISD::SEXTLOAD) {
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EVT MemVT = LoadNode->getMemoryVT();
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assert(!MemVT.isVector() && (MemVT == MVT::i16 || MemVT == MVT::i8));
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SDValue ShiftAmount =
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DAG.getConstant(VT.getSizeInBits() - MemVT.getSizeInBits(), DL,
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MVT::i32);
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SDValue NewLoad = DAG.getExtLoad(ISD::EXTLOAD, DL, VT, Chain, Ptr,
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LoadNode->getPointerInfo(), MemVT,
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LoadNode->isVolatile(),
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LoadNode->isNonTemporal(),
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LoadNode->isInvariant(),
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LoadNode->getAlignment());
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SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, NewLoad, ShiftAmount);
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SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Shl, ShiftAmount);
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SDValue Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, NewLoad,
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DAG.getValueType(MemVT));
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SDValue MergedValues[2] = { Sra, Chain };
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SDValue MergedValues[2] = { Res, Chain };
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return DAG.getMergeValues(MergedValues, DL);
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}
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@ -21,10 +21,8 @@ define void @load_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
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; FUNC-LABEL: {{^}}load_i8_sext:
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; R600: VTX_READ_8 [[DST:T[0-9]\.[XYZW]]], [[DST]]
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; R600: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]]
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; R600: 24
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; R600: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]]
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; R600: 24
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; R600: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST]], 0.0, literal
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; R600: 8
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; SI: buffer_load_sbyte
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define void @load_i8_sext(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
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entry:
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@ -50,14 +48,11 @@ entry:
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; FUNC-LABEL: {{^}}load_v2i8_sext:
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; R600-DAG: VTX_READ_8 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]]
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; R600-DAG: VTX_READ_8 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]]
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; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_X_CHAN:[XYZW]]], [[DST_X]]
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; R600-DAG: 24
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; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_X_CHAN]]
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; R600-DAG: 24
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; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Y_CHAN:[XYZW]]], [[DST_Y]]
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; R600-DAG: 24
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; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Y_CHAN]]
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; R600-DAG: 24
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; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_X]], 0.0, literal
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; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_Y]], 0.0, literal
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; R600-DAG: 8
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; R600-DAG: 8
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; SI: buffer_load_sbyte
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; SI: buffer_load_sbyte
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define void @load_v2i8_sext(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(1)* %in) {
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@ -90,22 +85,14 @@ entry:
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; R600-DAG: VTX_READ_8 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]]
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; R600-DAG: VTX_READ_8 [[DST_Z:T[0-9]\.[XYZW]]], [[DST_Z]]
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; R600-DAG: VTX_READ_8 [[DST_W:T[0-9]\.[XYZW]]], [[DST_W]]
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; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_X_CHAN:[XYZW]]], [[DST_X]]
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; R600-DAG: 24
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; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_X_CHAN]]
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; R600-DAG: 24
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; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Y_CHAN:[XYZW]]], [[DST_Y]]
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; R600-DAG: 24
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; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Y_CHAN]]
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; R600-DAG: 24
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; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Z_CHAN:[XYZW]]], [[DST_Z]]
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; R600-DAG: 24
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; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Z_CHAN]]
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; R600-DAG: 24
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; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_W_CHAN:[XYZW]]], [[DST_W]]
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; R600-DAG: 24
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; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_W_CHAN]]
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; R600-DAG: 24
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; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_X]], 0.0, literal
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; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_Y]], 0.0, literal
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; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_Z]], 0.0, literal
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; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_W]], 0.0, literal
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; R600-DAG: 8
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; R600-DAG: 8
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; R600-DAG: 8
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; R600-DAG: 8
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; SI: buffer_load_sbyte
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; SI: buffer_load_sbyte
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; SI: buffer_load_sbyte
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@ -132,9 +119,7 @@ entry:
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; FUNC-LABEL: {{^}}load_i16_sext:
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; R600: VTX_READ_16 [[DST:T[0-9]\.[XYZW]]], [[DST]]
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; R600: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]]
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; R600: 16
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; R600: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]]
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; R600: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST]], 0.0, literal
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; R600: 16
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; SI: buffer_load_sshort
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define void @load_i16_sext(i32 addrspace(1)* %out, i16 addrspace(1)* %in) {
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@ -161,13 +146,9 @@ entry:
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; FUNC-LABEL: {{^}}load_v2i16_sext:
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; R600-DAG: VTX_READ_16 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]]
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; R600-DAG: VTX_READ_16 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]]
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; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_X_CHAN:[XYZW]]], [[DST_X]]
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; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_X]], 0.0, literal
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; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_Y]], 0.0, literal
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; R600-DAG: 16
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; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_X_CHAN]]
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; R600-DAG: 16
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; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Y_CHAN:[XYZW]]], [[DST_Y]]
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; R600-DAG: 16
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; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Y_CHAN]]
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; R600-DAG: 16
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; SI: buffer_load_sshort
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; SI: buffer_load_sshort
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@ -201,21 +182,13 @@ entry:
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; R600-DAG: VTX_READ_16 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]]
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; R600-DAG: VTX_READ_16 [[DST_Z:T[0-9]\.[XYZW]]], [[DST_Z]]
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; R600-DAG: VTX_READ_16 [[DST_W:T[0-9]\.[XYZW]]], [[DST_W]]
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; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_X_CHAN:[XYZW]]], [[DST_X]]
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; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_X]], 0.0, literal
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; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_Y]], 0.0, literal
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; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_Z]], 0.0, literal
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; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_W]], 0.0, literal
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; R600-DAG: 16
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; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_X_CHAN]]
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; R600-DAG: 16
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; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Y_CHAN:[XYZW]]], [[DST_Y]]
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; R600-DAG: 16
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; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Y_CHAN]]
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; R600-DAG: 16
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; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Z_CHAN:[XYZW]]], [[DST_Z]]
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; R600-DAG: 16
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; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Z_CHAN]]
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; R600-DAG: 16
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; R600-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_W_CHAN:[XYZW]]], [[DST_W]]
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; R600-DAG: 16
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; R600-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_W_CHAN]]
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; R600-DAG: 16
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; SI: buffer_load_sshort
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; SI: buffer_load_sshort
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@ -356,10 +329,8 @@ entry:
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; Load a sign-extended i8 value
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; FUNC-LABEL: {{^}}load_const_i8_sext:
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; R600: VTX_READ_8 [[DST:T[0-9]\.[XYZW]]], [[DST]]
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; R600: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]]
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; R600: 24
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; R600: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]]
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; R600: 24
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; R600: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST]], 0.0, literal
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; R600: 8
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; SI: buffer_load_sbyte v{{[0-9]+}},
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define void @load_const_i8_sext(i32 addrspace(1)* %out, i8 addrspace(2)* %in) {
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entry:
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@ -397,9 +368,7 @@ entry:
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; Load a sign-extended i16 value
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; FUNC-LABEL: {{^}}load_const_i16_sext:
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; R600: VTX_READ_16 [[DST:T[0-9]\.[XYZW]]], [[DST]]
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; R600: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]]
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; R600: 16
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; R600: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]]
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; R600: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST]], 0.0, literal
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; R600: 16
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; SI: buffer_load_sshort
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define void @load_const_i16_sext(i32 addrspace(1)* %out, i16 addrspace(2)* %in) {
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@ -477,7 +446,7 @@ define void @load_i8_local(i32 addrspace(1)* %out, i8 addrspace(3)* %in) {
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; FUNC-LABEL: {{^}}load_i8_sext_local:
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; R600: LDS_UBYTE_READ_RET
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; R600: ASHR
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; R600: BFE_INT
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; SI-NOT: s_wqm_b64
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; SI: s_mov_b32 m0
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; SI: ds_read_i8
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@ -507,8 +476,8 @@ entry:
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; FUNC-LABEL: {{^}}load_v2i8_sext_local:
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; R600-DAG: LDS_UBYTE_READ_RET
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; R600-DAG: LDS_UBYTE_READ_RET
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; R600-DAG: ASHR
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; R600-DAG: ASHR
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; R600-DAG: BFE_INT
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; R600-DAG: BFE_INT
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; SI-NOT: s_wqm_b64
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; SI: s_mov_b32 m0
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; SI: ds_read_i8
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@ -545,10 +514,10 @@ entry:
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; R600-DAG: LDS_UBYTE_READ_RET
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; R600-DAG: LDS_UBYTE_READ_RET
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; R600-DAG: LDS_UBYTE_READ_RET
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; R600-DAG: ASHR
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; R600-DAG: ASHR
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; R600-DAG: ASHR
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; R600-DAG: ASHR
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; R600-DAG: BFE_INT
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; R600-DAG: BFE_INT
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; R600-DAG: BFE_INT
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; R600-DAG: BFE_INT
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; SI-NOT: s_wqm_b64
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; SI: s_mov_b32 m0
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; SI: ds_read_i8
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@ -579,7 +548,7 @@ entry:
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; FUNC-LABEL: {{^}}load_i16_sext_local:
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; R600: LDS_USHORT_READ_RET
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; R600: ASHR
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; R600: BFE_INT
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; SI-NOT: s_wqm_b64
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; SI: s_mov_b32 m0
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; SI: ds_read_i16
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@ -609,8 +578,8 @@ entry:
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; FUNC-LABEL: {{^}}load_v2i16_sext_local:
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; R600-DAG: LDS_USHORT_READ_RET
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; R600-DAG: LDS_USHORT_READ_RET
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; R600-DAG: ASHR
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; R600-DAG: ASHR
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; R600-DAG: BFE_INT
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; R600-DAG: BFE_INT
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; SI-NOT: s_wqm_b64
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; SI: s_mov_b32 m0
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; SI: ds_read_i16
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@ -647,10 +616,10 @@ entry:
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; R600-DAG: LDS_USHORT_READ_RET
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; R600-DAG: LDS_USHORT_READ_RET
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; R600-DAG: LDS_USHORT_READ_RET
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; R600-DAG: ASHR
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; R600-DAG: ASHR
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; R600-DAG: ASHR
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; R600-DAG: ASHR
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; R600-DAG: BFE_INT
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; R600-DAG: BFE_INT
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; R600-DAG: BFE_INT
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; R600-DAG: BFE_INT
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; SI-NOT: s_wqm_b64
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; SI: s_mov_b32 m0
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; SI: ds_read_i16
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