forked from OSchip/llvm-project
Revert "Revert "[AArch64][GlobalISel] Optimize conjunctions of compares to conditional compares.""
This reverts commit 55c181a6c7.
The original commit I made was an old patch, mea culpa. Committing the right
implementation with test case for the reported crash.
This commit is contained in:
Amara Emerson
parent
cde658fa1f
commit
b661470bce
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@ -14,6 +14,7 @@
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#ifndef LLVM_CODEGEN_GLOBALISEL_GENERICMACHINEINSTRS_H
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#define LLVM_CODEGEN_GLOBALISEL_GENERICMACHINEINSTRS_H
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#include "llvm/IR/Instructions.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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@ -226,6 +227,37 @@ public:
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}
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};
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/// Represent a G_ICMP or G_FCMP.
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class GAnyCmp : public GenericMachineInstr {
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public:
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CmpInst::Predicate getCond() const {
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return static_cast<CmpInst::Predicate>(getOperand(1).getPredicate());
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}
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Register getLHSReg() const { return getReg(2); }
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Register getRHSReg() const { return getReg(3); }
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static bool classof(const MachineInstr *MI) {
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return MI->getOpcode() == TargetOpcode::G_ICMP ||
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MI->getOpcode() == TargetOpcode::G_FCMP;
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}
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};
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/// Represent a G_ICMP.
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class GICmp : public GAnyCmp {
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public:
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static bool classof(const MachineInstr *MI) {
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return MI->getOpcode() == TargetOpcode::G_ICMP;
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}
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};
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/// Represent a G_FCMP.
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class GFCmp : public GAnyCmp {
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public:
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static bool classof(const MachineInstr *MI) {
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return MI->getOpcode() == TargetOpcode::G_FCMP;
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}
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};
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} // namespace llvm
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#endif // LLVM_CODEGEN_GLOBALISEL_GENERICMACHINEINSTRS_H
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@ -27,6 +27,7 @@
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#include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
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#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunction.h"
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@ -63,6 +64,7 @@ namespace {
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#include "AArch64GenGlobalISel.inc"
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#undef GET_GLOBALISEL_PREDICATE_BITSET
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class AArch64InstructionSelector : public InstructionSelector {
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public:
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AArch64InstructionSelector(const AArch64TargetMachine &TM,
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@ -294,6 +296,20 @@ private:
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emitOverflowOp(unsigned Opcode, Register Dst, MachineOperand &LHS,
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MachineOperand &RHS, MachineIRBuilder &MIRBuilder) const;
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/// Emit expression as a conjunction (a series of CCMP/CFCMP ops).
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/// In some cases this is even possible with OR operations in the expression.
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MachineInstr *emitConjunction(Register Val, AArch64CC::CondCode &OutCC,
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MachineIRBuilder &MIB) const;
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MachineInstr *emitConditionalComparison(Register LHS, Register RHS,
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CmpInst::Predicate CC,
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AArch64CC::CondCode Predicate,
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AArch64CC::CondCode OutCC,
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MachineIRBuilder &MIB) const;
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MachineInstr *emitConjunctionRec(Register Val, AArch64CC::CondCode &OutCC,
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bool Negate, Register CCOp,
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AArch64CC::CondCode Predicate,
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MachineIRBuilder &MIB) const;
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/// Emit a TB(N)Z instruction which tests \p Bit in \p TestReg.
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/// \p IsNegative is true if the test should be "not zero".
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/// This will also optimize the test bit instruction when possible.
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@ -425,7 +441,8 @@ private:
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void materializeLargeCMVal(MachineInstr &I, const Value *V, unsigned OpFlags);
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// Optimization methods.
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bool tryOptSelect(MachineInstr &MI);
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bool tryOptSelect(GSelect &Sel);
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bool tryOptSelectConjunction(GSelect &Sel, MachineInstr &CondMI);
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MachineInstr *tryFoldIntegerCompare(MachineOperand &LHS, MachineOperand &RHS,
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MachineOperand &Predicate,
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MachineIRBuilder &MIRBuilder) const;
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@ -1310,6 +1327,90 @@ static AArch64CC::CondCode changeICMPPredToAArch64CC(CmpInst::Predicate P) {
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}
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}
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/// changeFPCCToORAArch64CC - Convert an IR fp condition code to an AArch64 CC.
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static void changeFPCCToORAArch64CC(CmpInst::Predicate CC,
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AArch64CC::CondCode &CondCode,
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AArch64CC::CondCode &CondCode2) {
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CondCode2 = AArch64CC::AL;
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switch (CC) {
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default:
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llvm_unreachable("Unknown FP condition!");
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case CmpInst::FCMP_OEQ:
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CondCode = AArch64CC::EQ;
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break;
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case CmpInst::FCMP_OGT:
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CondCode = AArch64CC::GT;
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break;
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case CmpInst::FCMP_OGE:
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CondCode = AArch64CC::GE;
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break;
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case CmpInst::FCMP_OLT:
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CondCode = AArch64CC::MI;
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break;
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case CmpInst::FCMP_OLE:
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CondCode = AArch64CC::LS;
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break;
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case CmpInst::FCMP_ONE:
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CondCode = AArch64CC::MI;
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CondCode2 = AArch64CC::GT;
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break;
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case CmpInst::FCMP_ORD:
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CondCode = AArch64CC::VC;
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break;
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case CmpInst::FCMP_UNO:
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CondCode = AArch64CC::VS;
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break;
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case CmpInst::FCMP_UEQ:
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CondCode = AArch64CC::EQ;
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CondCode2 = AArch64CC::VS;
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break;
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case CmpInst::FCMP_UGT:
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CondCode = AArch64CC::HI;
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break;
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case CmpInst::FCMP_UGE:
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CondCode = AArch64CC::PL;
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break;
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case CmpInst::FCMP_ULT:
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CondCode = AArch64CC::LT;
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break;
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case CmpInst::FCMP_ULE:
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CondCode = AArch64CC::LE;
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break;
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case CmpInst::FCMP_UNE:
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CondCode = AArch64CC::NE;
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break;
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}
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}
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/// Convert an IR fp condition code to an AArch64 CC.
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/// This differs from changeFPCCToAArch64CC in that it returns cond codes that
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/// should be AND'ed instead of OR'ed.
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static void changeFPCCToANDAArch64CC(CmpInst::Predicate CC,
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AArch64CC::CondCode &CondCode,
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AArch64CC::CondCode &CondCode2) {
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CondCode2 = AArch64CC::AL;
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switch (CC) {
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default:
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changeFPCCToORAArch64CC(CC, CondCode, CondCode2);
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assert(CondCode2 == AArch64CC::AL);
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break;
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case CmpInst::FCMP_ONE:
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// (a one b)
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// == ((a olt b) || (a ogt b))
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// == ((a ord b) && (a une b))
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CondCode = AArch64CC::VC;
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CondCode2 = AArch64CC::NE;
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break;
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case CmpInst::FCMP_UEQ:
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// (a ueq b)
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// == ((a uno b) || (a oeq b))
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// == ((a ule b) && (a uge b))
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CondCode = AArch64CC::PL;
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CondCode2 = AArch64CC::LE;
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break;
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}
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}
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/// Return a register which can be used as a bit to test in a TB(N)Z.
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static Register getTestBitReg(Register Reg, uint64_t &Bit, bool &Invert,
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MachineRegisterInfo &MRI) {
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@ -3292,17 +3393,18 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
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return selectCopy(I, TII, MRI, TRI, RBI);
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case TargetOpcode::G_SELECT: {
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if (MRI.getType(I.getOperand(1).getReg()) != LLT::scalar(1)) {
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auto &Sel = cast<GSelect>(I);
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if (MRI.getType(Sel.getCondReg()) != LLT::scalar(1)) {
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LLVM_DEBUG(dbgs() << "G_SELECT cond has type: " << Ty
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<< ", expected: " << LLT::scalar(1) << '\n');
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return false;
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}
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const Register CondReg = I.getOperand(1).getReg();
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const Register TReg = I.getOperand(2).getReg();
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const Register FReg = I.getOperand(3).getReg();
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const Register CondReg = Sel.getCondReg();
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const Register TReg = Sel.getTrueReg();
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const Register FReg = Sel.getFalseReg();
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if (tryOptSelect(I))
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if (tryOptSelect(Sel))
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return true;
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// Make sure to use an unused vreg instead of wzr, so that the peephole
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@ -3311,9 +3413,9 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
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auto TstMI = MIB.buildInstr(AArch64::ANDSWri, {DeadVReg}, {CondReg})
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.addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
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constrainSelectedInstRegOperands(*TstMI, TII, TRI, RBI);
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if (!emitSelect(I.getOperand(0).getReg(), TReg, FReg, AArch64CC::NE, MIB))
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if (!emitSelect(Sel.getReg(0), TReg, FReg, AArch64CC::NE, MIB))
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return false;
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I.eraseFromParent();
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Sel.eraseFromParent();
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return true;
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}
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case TargetOpcode::G_ICMP: {
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@ -4702,7 +4804,256 @@ AArch64InstructionSelector::emitOverflowOp(unsigned Opcode, Register Dst,
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}
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}
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bool AArch64InstructionSelector::tryOptSelect(MachineInstr &I) {
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/// Returns true if @p Val is a tree of AND/OR/CMP operations that can be
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/// expressed as a conjunction.
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/// \param CanNegate Set to true if we can negate the whole sub-tree just by
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/// changing the conditions on the CMP tests.
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/// (this means we can call emitConjunctionRec() with
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/// Negate==true on this sub-tree)
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/// \param MustBeFirst Set to true if this subtree needs to be negated and we
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/// cannot do the negation naturally. We are required to
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/// emit the subtree first in this case.
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/// \param WillNegate Is true if are called when the result of this
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/// subexpression must be negated. This happens when the
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/// outer expression is an OR. We can use this fact to know
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/// that we have a double negation (or (or ...) ...) that
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/// can be implemented for free.
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static bool canEmitConjunction(Register Val, bool &CanNegate, bool &MustBeFirst,
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bool WillNegate, MachineRegisterInfo &MRI,
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unsigned Depth = 0) {
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if (!MRI.hasOneNonDBGUse(Val))
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return false;
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MachineInstr *ValDef = MRI.getVRegDef(Val);
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unsigned Opcode = ValDef->getOpcode();
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if (Opcode == TargetOpcode::G_TRUNC) {
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// Look through a trunc.
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Val = ValDef->getOperand(1).getReg();
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ValDef = MRI.getVRegDef(Val);
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Opcode = ValDef->getOpcode();
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}
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if (isa<GAnyCmp>(ValDef)) {
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CanNegate = true;
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MustBeFirst = false;
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return true;
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}
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// Protect against exponential runtime and stack overflow.
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if (Depth > 6)
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return false;
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if (Opcode == TargetOpcode::G_AND || Opcode == TargetOpcode::G_OR) {
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bool IsOR = Opcode == TargetOpcode::G_OR;
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Register O0 = ValDef->getOperand(1).getReg();
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Register O1 = ValDef->getOperand(2).getReg();
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bool CanNegateL;
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bool MustBeFirstL;
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if (!canEmitConjunction(O0, CanNegateL, MustBeFirstL, IsOR, MRI, Depth + 1))
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return false;
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bool CanNegateR;
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bool MustBeFirstR;
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if (!canEmitConjunction(O1, CanNegateR, MustBeFirstR, IsOR, MRI, Depth + 1))
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return false;
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if (MustBeFirstL && MustBeFirstR)
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return false;
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if (IsOR) {
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// For an OR expression we need to be able to naturally negate at least
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// one side or we cannot do the transformation at all.
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if (!CanNegateL && !CanNegateR)
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return false;
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// If we the result of the OR will be negated and we can naturally negate
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// the leaves, then this sub-tree as a whole negates naturally.
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CanNegate = WillNegate && CanNegateL && CanNegateR;
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// If we cannot naturally negate the whole sub-tree, then this must be
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// emitted first.
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MustBeFirst = !CanNegate;
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} else {
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assert(Opcode == TargetOpcode::G_AND && "Must be G_AND");
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// We cannot naturally negate an AND operation.
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CanNegate = false;
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MustBeFirst = MustBeFirstL || MustBeFirstR;
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}
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return true;
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}
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return false;
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}
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MachineInstr *AArch64InstructionSelector::emitConditionalComparison(
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Register LHS, Register RHS, CmpInst::Predicate CC,
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AArch64CC::CondCode Predicate, AArch64CC::CondCode OutCC,
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MachineIRBuilder &MIB) const {
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// TODO: emit CMN as an optimization.
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auto &MRI = *MIB.getMRI();
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LLT OpTy = MRI.getType(LHS);
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assert(OpTy.getSizeInBits() == 32 || OpTy.getSizeInBits() == 64);
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unsigned CCmpOpc;
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if (CmpInst::isIntPredicate(CC)) {
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CCmpOpc = OpTy.getSizeInBits() == 32 ? AArch64::CCMPWr : AArch64::CCMPXr;
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} else {
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switch (OpTy.getSizeInBits()) {
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case 16:
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CCmpOpc = AArch64::FCCMPHrr;
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break;
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case 32:
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CCmpOpc = AArch64::FCCMPSrr;
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break;
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case 64:
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CCmpOpc = AArch64::FCCMPDrr;
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break;
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default:
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return nullptr;
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}
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}
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AArch64CC::CondCode InvOutCC = AArch64CC::getInvertedCondCode(OutCC);
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unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(InvOutCC);
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auto CCmp =
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MIB.buildInstr(CCmpOpc, {}, {LHS, RHS}).addImm(NZCV).addImm(Predicate);
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constrainSelectedInstRegOperands(*CCmp, TII, TRI, RBI);
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return &*CCmp;
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}
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MachineInstr *AArch64InstructionSelector::emitConjunctionRec(
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Register Val, AArch64CC::CondCode &OutCC, bool Negate, Register CCOp,
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AArch64CC::CondCode Predicate, MachineIRBuilder &MIB) const {
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// We're at a tree leaf, produce a conditional comparison operation.
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auto &MRI = *MIB.getMRI();
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MachineInstr *ValDef = MRI.getVRegDef(Val);
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unsigned Opcode = ValDef->getOpcode();
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if (Opcode == TargetOpcode::G_TRUNC) {
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// Look through a trunc.
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Val = ValDef->getOperand(1).getReg();
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ValDef = MRI.getVRegDef(Val);
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Opcode = ValDef->getOpcode();
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}
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if (auto *Cmp = dyn_cast<GAnyCmp>(ValDef)) {
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Register LHS = Cmp->getLHSReg();
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Register RHS = Cmp->getRHSReg();
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CmpInst::Predicate CC = Cmp->getCond();
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if (Negate)
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CC = CmpInst::getInversePredicate(CC);
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if (isa<GICmp>(Cmp)) {
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OutCC = changeICMPPredToAArch64CC(CC);
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} else {
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// Handle special FP cases.
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AArch64CC::CondCode ExtraCC;
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changeFPCCToANDAArch64CC(CC, OutCC, ExtraCC);
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// Some floating point conditions can't be tested with a single condition
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// code. Construct an additional comparison in this case.
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if (ExtraCC != AArch64CC::AL) {
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MachineInstr *ExtraCmp;
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if (!CCOp)
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ExtraCmp = emitFPCompare(LHS, RHS, MIB, CC);
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else
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ExtraCmp =
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emitConditionalComparison(LHS, RHS, CC, Predicate, ExtraCC, MIB);
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CCOp = ExtraCmp->getOperand(0).getReg();
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Predicate = ExtraCC;
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}
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}
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// Produce a normal comparison if we are first in the chain
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if (!CCOp) {
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auto Dst = MRI.cloneVirtualRegister(LHS);
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if (isa<GICmp>(Cmp))
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return emitSUBS(Dst, Cmp->getOperand(2), Cmp->getOperand(3), MIB);
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return emitFPCompare(Cmp->getOperand(2).getReg(),
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Cmp->getOperand(3).getReg(), MIB);
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}
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// Otherwise produce a ccmp.
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return emitConditionalComparison(LHS, RHS, CC, Predicate, OutCC, MIB);
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}
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assert(MRI.hasOneNonDBGUse(Val) && "Valid conjunction/disjunction tree");
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bool IsOR = Opcode == TargetOpcode::G_OR;
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Register LHS = ValDef->getOperand(1).getReg();
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bool CanNegateL;
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bool MustBeFirstL;
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bool ValidL = canEmitConjunction(LHS, CanNegateL, MustBeFirstL, IsOR, MRI);
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assert(ValidL && "Valid conjunction/disjunction tree");
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(void)ValidL;
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Register RHS = ValDef->getOperand(2).getReg();
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bool CanNegateR;
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bool MustBeFirstR;
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bool ValidR = canEmitConjunction(RHS, CanNegateR, MustBeFirstR, IsOR, MRI);
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assert(ValidR && "Valid conjunction/disjunction tree");
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(void)ValidR;
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// Swap sub-tree that must come first to the right side.
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if (MustBeFirstL) {
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assert(!MustBeFirstR && "Valid conjunction/disjunction tree");
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std::swap(LHS, RHS);
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std::swap(CanNegateL, CanNegateR);
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std::swap(MustBeFirstL, MustBeFirstR);
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}
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bool NegateR;
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bool NegateAfterR;
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bool NegateL;
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bool NegateAfterAll;
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if (Opcode == TargetOpcode::G_OR) {
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// Swap the sub-tree that we can negate naturally to the left.
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if (!CanNegateL) {
|
||||
assert(CanNegateR && "at least one side must be negatable");
|
||||
assert(!MustBeFirstR && "invalid conjunction/disjunction tree");
|
||||
assert(!Negate);
|
||||
std::swap(LHS, RHS);
|
||||
NegateR = false;
|
||||
NegateAfterR = true;
|
||||
} else {
|
||||
// Negate the left sub-tree if possible, otherwise negate the result.
|
||||
NegateR = CanNegateR;
|
||||
NegateAfterR = !CanNegateR;
|
||||
}
|
||||
NegateL = true;
|
||||
NegateAfterAll = !Negate;
|
||||
} else {
|
||||
assert(Opcode == TargetOpcode::G_AND &&
|
||||
"Valid conjunction/disjunction tree");
|
||||
assert(!Negate && "Valid conjunction/disjunction tree");
|
||||
|
||||
NegateL = false;
|
||||
NegateR = false;
|
||||
NegateAfterR = false;
|
||||
NegateAfterAll = false;
|
||||
}
|
||||
|
||||
// Emit sub-trees.
|
||||
AArch64CC::CondCode RHSCC;
|
||||
MachineInstr *CmpR =
|
||||
emitConjunctionRec(RHS, RHSCC, NegateR, CCOp, Predicate, MIB);
|
||||
if (NegateAfterR)
|
||||
RHSCC = AArch64CC::getInvertedCondCode(RHSCC);
|
||||
MachineInstr *CmpL = emitConjunctionRec(
|
||||
LHS, OutCC, NegateL, CmpR->getOperand(0).getReg(), RHSCC, MIB);
|
||||
if (NegateAfterAll)
|
||||
OutCC = AArch64CC::getInvertedCondCode(OutCC);
|
||||
return CmpL;
|
||||
}
|
||||
|
||||
MachineInstr *AArch64InstructionSelector::emitConjunction(
|
||||
Register Val, AArch64CC::CondCode &OutCC, MachineIRBuilder &MIB) const {
|
||||
bool DummyCanNegate;
|
||||
bool DummyMustBeFirst;
|
||||
if (!canEmitConjunction(Val, DummyCanNegate, DummyMustBeFirst, false,
|
||||
*MIB.getMRI()))
|
||||
return nullptr;
|
||||
return emitConjunctionRec(Val, OutCC, false, Register(), AArch64CC::AL, MIB);
|
||||
}
|
||||
|
||||
bool AArch64InstructionSelector::tryOptSelectConjunction(GSelect &SelI,
|
||||
MachineInstr &CondMI) {
|
||||
AArch64CC::CondCode AArch64CC;
|
||||
MachineInstr *ConjMI = emitConjunction(SelI.getCondReg(), AArch64CC, MIB);
|
||||
if (!ConjMI)
|
||||
return false;
|
||||
|
||||
emitSelect(SelI.getReg(0), SelI.getTrueReg(), SelI.getFalseReg(), AArch64CC, MIB);
|
||||
SelI.eraseFromParent();
|
||||
return true;
|
||||
}
|
||||
|
||||
bool AArch64InstructionSelector::tryOptSelect(GSelect &I) {
|
||||
MachineRegisterInfo &MRI = *MIB.getMRI();
|
||||
// We want to recognize this pattern:
|
||||
//
|
||||
|
|
@ -4755,8 +5106,11 @@ bool AArch64InstructionSelector::tryOptSelect(MachineInstr &I) {
|
|||
return false;
|
||||
|
||||
unsigned CondOpc = CondDef->getOpcode();
|
||||
if (CondOpc != TargetOpcode::G_ICMP && CondOpc != TargetOpcode::G_FCMP)
|
||||
if (CondOpc != TargetOpcode::G_ICMP && CondOpc != TargetOpcode::G_FCMP) {
|
||||
if (tryOptSelectConjunction(I, *CondDef))
|
||||
return true;
|
||||
return false;
|
||||
}
|
||||
|
||||
AArch64CC::CondCode CondCode;
|
||||
if (CondOpc == TargetOpcode::G_ICMP) {
|
||||
|
|
|
|||
|
|
@ -569,14 +569,10 @@ define i64 @select_and(i32 %w0, i32 %w1, i64 %x2, i64 %x3) {
|
|||
;
|
||||
; GISEL-LABEL: select_and:
|
||||
; GISEL: ; %bb.0:
|
||||
; GISEL-NEXT: cmp w0, w1
|
||||
; GISEL-NEXT: cset w8, lt
|
||||
; GISEL-NEXT: mov w9, #5
|
||||
; GISEL-NEXT: cmp w9, w1
|
||||
; GISEL-NEXT: cset w9, ne
|
||||
; GISEL-NEXT: and w8, w8, w9
|
||||
; GISEL-NEXT: tst w8, #0x1
|
||||
; GISEL-NEXT: csel x0, x2, x3, ne
|
||||
; GISEL-NEXT: mov w8, #5
|
||||
; GISEL-NEXT: cmp w8, w1
|
||||
; GISEL-NEXT: ccmp w0, w1, #0, ne
|
||||
; GISEL-NEXT: csel x0, x2, x3, lt
|
||||
; GISEL-NEXT: ret
|
||||
%1 = icmp slt i32 %w0, %w1
|
||||
%2 = icmp ne i32 5, %w1
|
||||
|
|
@ -595,14 +591,10 @@ define i64 @select_or(i32 %w0, i32 %w1, i64 %x2, i64 %x3) {
|
|||
;
|
||||
; GISEL-LABEL: select_or:
|
||||
; GISEL: ; %bb.0:
|
||||
; GISEL-NEXT: cmp w0, w1
|
||||
; GISEL-NEXT: cset w8, lt
|
||||
; GISEL-NEXT: mov w9, #5
|
||||
; GISEL-NEXT: cmp w9, w1
|
||||
; GISEL-NEXT: cset w9, ne
|
||||
; GISEL-NEXT: orr w8, w8, w9
|
||||
; GISEL-NEXT: tst w8, #0x1
|
||||
; GISEL-NEXT: csel x0, x2, x3, ne
|
||||
; GISEL-NEXT: mov w8, #5
|
||||
; GISEL-NEXT: cmp w8, w1
|
||||
; GISEL-NEXT: ccmp w0, w1, #8, eq
|
||||
; GISEL-NEXT: csel x0, x2, x3, lt
|
||||
; GISEL-NEXT: ret
|
||||
%1 = icmp slt i32 %w0, %w1
|
||||
%2 = icmp ne i32 5, %w1
|
||||
|
|
@ -611,6 +603,28 @@ define i64 @select_or(i32 %w0, i32 %w1, i64 %x2, i64 %x3) {
|
|||
ret i64 %sel
|
||||
}
|
||||
|
||||
define float @select_or_float(i32 %w0, i32 %w1, float %x2, float %x3) {
|
||||
; CHECK-LABEL: select_or_float:
|
||||
; CHECK: ; %bb.0:
|
||||
; CHECK-NEXT: cmp w1, #5
|
||||
; CHECK-NEXT: ccmp w0, w1, #8, eq
|
||||
; CHECK-NEXT: fcsel s0, s0, s1, lt
|
||||
; CHECK-NEXT: ret
|
||||
;
|
||||
; GISEL-LABEL: select_or_float:
|
||||
; GISEL: ; %bb.0:
|
||||
; GISEL-NEXT: mov w8, #5
|
||||
; GISEL-NEXT: cmp w8, w1
|
||||
; GISEL-NEXT: ccmp w0, w1, #8, eq
|
||||
; GISEL-NEXT: fcsel s0, s0, s1, lt
|
||||
; GISEL-NEXT: ret
|
||||
%1 = icmp slt i32 %w0, %w1
|
||||
%2 = icmp ne i32 5, %w1
|
||||
%3 = or i1 %1, %2
|
||||
%sel = select i1 %3, float %x2,float %x3
|
||||
ret float %sel
|
||||
}
|
||||
|
||||
define i64 @gccbug(i64 %x0, i64 %x1) {
|
||||
; CHECK-LABEL: gccbug:
|
||||
; CHECK: ; %bb.0:
|
||||
|
|
@ -623,17 +637,12 @@ define i64 @gccbug(i64 %x0, i64 %x1) {
|
|||
;
|
||||
; GISEL-LABEL: gccbug:
|
||||
; GISEL: ; %bb.0:
|
||||
; GISEL-NEXT: cmp x1, #0
|
||||
; GISEL-NEXT: cset w8, eq
|
||||
; GISEL-NEXT: mov w9, #2
|
||||
; GISEL-NEXT: mov w8, #2
|
||||
; GISEL-NEXT: mov w9, #4
|
||||
; GISEL-NEXT: cmp x0, #2
|
||||
; GISEL-NEXT: cset w10, eq
|
||||
; GISEL-NEXT: cmp x0, #4
|
||||
; GISEL-NEXT: cset w11, eq
|
||||
; GISEL-NEXT: orr w10, w11, w10
|
||||
; GISEL-NEXT: and w8, w10, w8
|
||||
; GISEL-NEXT: tst w8, #0x1
|
||||
; GISEL-NEXT: csinc x0, x9, xzr, ne
|
||||
; GISEL-NEXT: ccmp x0, x9, #4, ne
|
||||
; GISEL-NEXT: ccmp x1, xzr, #0, eq
|
||||
; GISEL-NEXT: csinc x0, x8, xzr, eq
|
||||
; GISEL-NEXT: ret
|
||||
%cmp0 = icmp eq i64 %x1, 0
|
||||
%cmp1 = icmp eq i64 %x0, 2
|
||||
|
|
@ -658,19 +667,13 @@ define i32 @select_ororand(i32 %w0, i32 %w1, i32 %w2, i32 %w3) {
|
|||
;
|
||||
; GISEL-LABEL: select_ororand:
|
||||
; GISEL: ; %bb.0:
|
||||
; GISEL-NEXT: cmp w0, #0
|
||||
; GISEL-NEXT: cset w8, eq
|
||||
; GISEL-NEXT: cmp w1, #13
|
||||
; GISEL-NEXT: cset w9, hi
|
||||
; GISEL-NEXT: cmp w2, #2
|
||||
; GISEL-NEXT: cset w10, lt
|
||||
; GISEL-NEXT: mov w8, #13
|
||||
; GISEL-NEXT: mov w9, #2
|
||||
; GISEL-NEXT: cmp w3, #4
|
||||
; GISEL-NEXT: cset w11, gt
|
||||
; GISEL-NEXT: orr w8, w8, w9
|
||||
; GISEL-NEXT: and w9, w10, w11
|
||||
; GISEL-NEXT: orr w8, w8, w9
|
||||
; GISEL-NEXT: tst w8, #0x1
|
||||
; GISEL-NEXT: csel w0, w3, wzr, ne
|
||||
; GISEL-NEXT: ccmp w2, w9, #0, gt
|
||||
; GISEL-NEXT: ccmp w1, w8, #2, ge
|
||||
; GISEL-NEXT: ccmp w0, wzr, #4, ls
|
||||
; GISEL-NEXT: csel w0, w3, wzr, eq
|
||||
; GISEL-NEXT: ret
|
||||
%c0 = icmp eq i32 %w0, 0
|
||||
%c1 = icmp ugt i32 %w1, 13
|
||||
|
|
@ -694,16 +697,10 @@ define i32 @select_andor(i32 %v1, i32 %v2, i32 %v3) {
|
|||
;
|
||||
; GISEL-LABEL: select_andor:
|
||||
; GISEL: ; %bb.0:
|
||||
; GISEL-NEXT: cmp w0, w1
|
||||
; GISEL-NEXT: cset w8, eq
|
||||
; GISEL-NEXT: cmp w1, w2
|
||||
; GISEL-NEXT: cset w9, ge
|
||||
; GISEL-NEXT: cmp w0, #0
|
||||
; GISEL-NEXT: cset w10, eq
|
||||
; GISEL-NEXT: orr w9, w10, w9
|
||||
; GISEL-NEXT: and w8, w9, w8
|
||||
; GISEL-NEXT: tst w8, #0x1
|
||||
; GISEL-NEXT: csel w0, w0, w1, ne
|
||||
; GISEL-NEXT: ccmp w0, wzr, #4, lt
|
||||
; GISEL-NEXT: ccmp w0, w1, #0, eq
|
||||
; GISEL-NEXT: csel w0, w0, w1, eq
|
||||
; GISEL-NEXT: ret
|
||||
%c0 = icmp eq i32 %v1, %v2
|
||||
%c1 = icmp sge i32 %v2, %v3
|
||||
|
|
@ -872,14 +869,9 @@ define i32 @select_and_olt_one(double %v0, double %v1, double %v2, double %v3, i
|
|||
; GISEL-LABEL: select_and_olt_one:
|
||||
; GISEL: ; %bb.0:
|
||||
; GISEL-NEXT: fcmp d0, d1
|
||||
; GISEL-NEXT: cset w8, mi
|
||||
; GISEL-NEXT: fcmp d2, d3
|
||||
; GISEL-NEXT: cset w9, mi
|
||||
; GISEL-NEXT: cset w10, gt
|
||||
; GISEL-NEXT: orr w9, w9, w10
|
||||
; GISEL-NEXT: and w8, w9, w8
|
||||
; GISEL-NEXT: tst w8, #0x1
|
||||
; GISEL-NEXT: csel w0, w0, w1, ne
|
||||
; GISEL-NEXT: fccmp d2, d3, #4, mi
|
||||
; GISEL-NEXT: fccmp d2, d3, #1, ne
|
||||
; GISEL-NEXT: csel w0, w0, w1, vc
|
||||
; GISEL-NEXT: ret
|
||||
%c0 = fcmp olt double %v0, %v1
|
||||
%c1 = fcmp one double %v2, %v3
|
||||
|
|
@ -900,14 +892,9 @@ define i32 @select_and_one_olt(double %v0, double %v1, double %v2, double %v3, i
|
|||
; GISEL-LABEL: select_and_one_olt:
|
||||
; GISEL: ; %bb.0:
|
||||
; GISEL-NEXT: fcmp d0, d1
|
||||
; GISEL-NEXT: cset w8, mi
|
||||
; GISEL-NEXT: cset w9, gt
|
||||
; GISEL-NEXT: orr w8, w8, w9
|
||||
; GISEL-NEXT: fcmp d2, d3
|
||||
; GISEL-NEXT: cset w9, mi
|
||||
; GISEL-NEXT: and w8, w9, w8
|
||||
; GISEL-NEXT: tst w8, #0x1
|
||||
; GISEL-NEXT: csel w0, w0, w1, ne
|
||||
; GISEL-NEXT: fccmp d0, d1, #1, ne
|
||||
; GISEL-NEXT: fccmp d2, d3, #0, vc
|
||||
; GISEL-NEXT: csel w0, w0, w1, mi
|
||||
; GISEL-NEXT: ret
|
||||
%c0 = fcmp one double %v0, %v1
|
||||
%c1 = fcmp olt double %v2, %v3
|
||||
|
|
@ -928,14 +915,9 @@ define i32 @select_and_olt_ueq(double %v0, double %v1, double %v2, double %v3, i
|
|||
; GISEL-LABEL: select_and_olt_ueq:
|
||||
; GISEL: ; %bb.0:
|
||||
; GISEL-NEXT: fcmp d0, d1
|
||||
; GISEL-NEXT: cset w8, mi
|
||||
; GISEL-NEXT: fcmp d2, d3
|
||||
; GISEL-NEXT: cset w9, eq
|
||||
; GISEL-NEXT: cset w10, vs
|
||||
; GISEL-NEXT: orr w9, w9, w10
|
||||
; GISEL-NEXT: and w8, w9, w8
|
||||
; GISEL-NEXT: tst w8, #0x1
|
||||
; GISEL-NEXT: csel w0, w0, w1, ne
|
||||
; GISEL-NEXT: fccmp d2, d3, #0, mi
|
||||
; GISEL-NEXT: fccmp d2, d3, #8, le
|
||||
; GISEL-NEXT: csel w0, w0, w1, pl
|
||||
; GISEL-NEXT: ret
|
||||
%c0 = fcmp olt double %v0, %v1
|
||||
%c1 = fcmp ueq double %v2, %v3
|
||||
|
|
@ -956,14 +938,9 @@ define i32 @select_and_ueq_olt(double %v0, double %v1, double %v2, double %v3, i
|
|||
; GISEL-LABEL: select_and_ueq_olt:
|
||||
; GISEL: ; %bb.0:
|
||||
; GISEL-NEXT: fcmp d0, d1
|
||||
; GISEL-NEXT: cset w8, eq
|
||||
; GISEL-NEXT: cset w9, vs
|
||||
; GISEL-NEXT: orr w8, w8, w9
|
||||
; GISEL-NEXT: fcmp d2, d3
|
||||
; GISEL-NEXT: cset w9, mi
|
||||
; GISEL-NEXT: and w8, w9, w8
|
||||
; GISEL-NEXT: tst w8, #0x1
|
||||
; GISEL-NEXT: csel w0, w0, w1, ne
|
||||
; GISEL-NEXT: fccmp d0, d1, #8, le
|
||||
; GISEL-NEXT: fccmp d2, d3, #0, pl
|
||||
; GISEL-NEXT: csel w0, w0, w1, mi
|
||||
; GISEL-NEXT: ret
|
||||
%c0 = fcmp ueq double %v0, %v1
|
||||
%c1 = fcmp olt double %v2, %v3
|
||||
|
|
@ -984,14 +961,9 @@ define i32 @select_or_olt_one(double %v0, double %v1, double %v2, double %v3, i3
|
|||
; GISEL-LABEL: select_or_olt_one:
|
||||
; GISEL: ; %bb.0:
|
||||
; GISEL-NEXT: fcmp d0, d1
|
||||
; GISEL-NEXT: cset w8, mi
|
||||
; GISEL-NEXT: fcmp d2, d3
|
||||
; GISEL-NEXT: cset w9, mi
|
||||
; GISEL-NEXT: cset w10, gt
|
||||
; GISEL-NEXT: orr w9, w9, w10
|
||||
; GISEL-NEXT: orr w8, w9, w8
|
||||
; GISEL-NEXT: tst w8, #0x1
|
||||
; GISEL-NEXT: csel w0, w0, w1, ne
|
||||
; GISEL-NEXT: fccmp d2, d3, #0, pl
|
||||
; GISEL-NEXT: fccmp d2, d3, #8, le
|
||||
; GISEL-NEXT: csel w0, w0, w1, mi
|
||||
; GISEL-NEXT: ret
|
||||
%c0 = fcmp olt double %v0, %v1
|
||||
%c1 = fcmp one double %v2, %v3
|
||||
|
|
@ -1012,14 +984,9 @@ define i32 @select_or_one_olt(double %v0, double %v1, double %v2, double %v3, i3
|
|||
; GISEL-LABEL: select_or_one_olt:
|
||||
; GISEL: ; %bb.0:
|
||||
; GISEL-NEXT: fcmp d0, d1
|
||||
; GISEL-NEXT: cset w8, mi
|
||||
; GISEL-NEXT: cset w9, gt
|
||||
; GISEL-NEXT: orr w8, w8, w9
|
||||
; GISEL-NEXT: fcmp d2, d3
|
||||
; GISEL-NEXT: cset w9, mi
|
||||
; GISEL-NEXT: orr w8, w9, w8
|
||||
; GISEL-NEXT: tst w8, #0x1
|
||||
; GISEL-NEXT: csel w0, w0, w1, ne
|
||||
; GISEL-NEXT: fccmp d0, d1, #8, le
|
||||
; GISEL-NEXT: fccmp d2, d3, #8, pl
|
||||
; GISEL-NEXT: csel w0, w0, w1, mi
|
||||
; GISEL-NEXT: ret
|
||||
%c0 = fcmp one double %v0, %v1
|
||||
%c1 = fcmp olt double %v2, %v3
|
||||
|
|
@ -1040,14 +1007,9 @@ define i32 @select_or_olt_ueq(double %v0, double %v1, double %v2, double %v3, i3
|
|||
; GISEL-LABEL: select_or_olt_ueq:
|
||||
; GISEL: ; %bb.0:
|
||||
; GISEL-NEXT: fcmp d0, d1
|
||||
; GISEL-NEXT: cset w8, mi
|
||||
; GISEL-NEXT: fcmp d2, d3
|
||||
; GISEL-NEXT: cset w9, eq
|
||||
; GISEL-NEXT: cset w10, vs
|
||||
; GISEL-NEXT: orr w9, w9, w10
|
||||
; GISEL-NEXT: orr w8, w9, w8
|
||||
; GISEL-NEXT: tst w8, #0x1
|
||||
; GISEL-NEXT: csel w0, w0, w1, ne
|
||||
; GISEL-NEXT: fccmp d2, d3, #4, pl
|
||||
; GISEL-NEXT: fccmp d2, d3, #1, ne
|
||||
; GISEL-NEXT: csel w0, w0, w1, vs
|
||||
; GISEL-NEXT: ret
|
||||
%c0 = fcmp olt double %v0, %v1
|
||||
%c1 = fcmp ueq double %v2, %v3
|
||||
|
|
@ -1068,14 +1030,9 @@ define i32 @select_or_ueq_olt(double %v0, double %v1, double %v2, double %v3, i3
|
|||
; GISEL-LABEL: select_or_ueq_olt:
|
||||
; GISEL: ; %bb.0:
|
||||
; GISEL-NEXT: fcmp d0, d1
|
||||
; GISEL-NEXT: cset w8, eq
|
||||
; GISEL-NEXT: cset w9, vs
|
||||
; GISEL-NEXT: orr w8, w8, w9
|
||||
; GISEL-NEXT: fcmp d2, d3
|
||||
; GISEL-NEXT: cset w9, mi
|
||||
; GISEL-NEXT: orr w8, w9, w8
|
||||
; GISEL-NEXT: tst w8, #0x1
|
||||
; GISEL-NEXT: csel w0, w0, w1, ne
|
||||
; GISEL-NEXT: fccmp d0, d1, #1, ne
|
||||
; GISEL-NEXT: fccmp d2, d3, #8, vc
|
||||
; GISEL-NEXT: csel w0, w0, w1, mi
|
||||
; GISEL-NEXT: ret
|
||||
%c0 = fcmp ueq double %v0, %v1
|
||||
%c1 = fcmp olt double %v2, %v3
|
||||
|
|
@ -1097,17 +1054,10 @@ define i32 @select_or_olt_ogt_ueq(double %v0, double %v1, double %v2, double %v3
|
|||
; GISEL-LABEL: select_or_olt_ogt_ueq:
|
||||
; GISEL: ; %bb.0:
|
||||
; GISEL-NEXT: fcmp d0, d1
|
||||
; GISEL-NEXT: cset w8, mi
|
||||
; GISEL-NEXT: fcmp d2, d3
|
||||
; GISEL-NEXT: cset w9, gt
|
||||
; GISEL-NEXT: fcmp d4, d5
|
||||
; GISEL-NEXT: cset w10, eq
|
||||
; GISEL-NEXT: cset w11, vs
|
||||
; GISEL-NEXT: orr w10, w10, w11
|
||||
; GISEL-NEXT: orr w8, w9, w8
|
||||
; GISEL-NEXT: orr w8, w10, w8
|
||||
; GISEL-NEXT: tst w8, #0x1
|
||||
; GISEL-NEXT: csel w0, w0, w1, ne
|
||||
; GISEL-NEXT: fccmp d2, d3, #0, pl
|
||||
; GISEL-NEXT: fccmp d4, d5, #4, le
|
||||
; GISEL-NEXT: fccmp d4, d5, #1, ne
|
||||
; GISEL-NEXT: csel w0, w0, w1, vs
|
||||
; GISEL-NEXT: ret
|
||||
%c0 = fcmp olt double %v0, %v1
|
||||
%c1 = fcmp ogt double %v2, %v3
|
||||
|
|
@ -1131,17 +1081,10 @@ define i32 @select_or_olt_ueq_ogt(double %v0, double %v1, double %v2, double %v3
|
|||
; GISEL-LABEL: select_or_olt_ueq_ogt:
|
||||
; GISEL: ; %bb.0:
|
||||
; GISEL-NEXT: fcmp d0, d1
|
||||
; GISEL-NEXT: cset w8, mi
|
||||
; GISEL-NEXT: fcmp d2, d3
|
||||
; GISEL-NEXT: cset w9, eq
|
||||
; GISEL-NEXT: cset w10, vs
|
||||
; GISEL-NEXT: orr w9, w9, w10
|
||||
; GISEL-NEXT: fcmp d4, d5
|
||||
; GISEL-NEXT: cset w10, gt
|
||||
; GISEL-NEXT: orr w8, w9, w8
|
||||
; GISEL-NEXT: orr w8, w10, w8
|
||||
; GISEL-NEXT: tst w8, #0x1
|
||||
; GISEL-NEXT: csel w0, w0, w1, ne
|
||||
; GISEL-NEXT: fccmp d2, d3, #4, pl
|
||||
; GISEL-NEXT: fccmp d2, d3, #1, ne
|
||||
; GISEL-NEXT: fccmp d4, d5, #0, vc
|
||||
; GISEL-NEXT: csel w0, w0, w1, gt
|
||||
; GISEL-NEXT: ret
|
||||
%c0 = fcmp olt double %v0, %v1
|
||||
%c1 = fcmp ueq double %v2, %v3
|
||||
|
|
@ -1170,15 +1113,11 @@ define i32 @half_select_and_olt_oge(half %v0, half %v1, half %v2, half %v3, i32
|
|||
; GISEL: ; %bb.0:
|
||||
; GISEL-NEXT: fcvt s0, h0
|
||||
; GISEL-NEXT: fcvt s1, h1
|
||||
; GISEL-NEXT: fcvt s2, h2
|
||||
; GISEL-NEXT: fcvt s3, h3
|
||||
; GISEL-NEXT: fcmp s0, s1
|
||||
; GISEL-NEXT: cset w8, mi
|
||||
; GISEL-NEXT: fcvt s0, h2
|
||||
; GISEL-NEXT: fcvt s1, h3
|
||||
; GISEL-NEXT: fcmp s0, s1
|
||||
; GISEL-NEXT: cset w9, ge
|
||||
; GISEL-NEXT: and w8, w9, w8
|
||||
; GISEL-NEXT: tst w8, #0x1
|
||||
; GISEL-NEXT: csel w0, w0, w1, ne
|
||||
; GISEL-NEXT: fccmp s2, s3, #8, mi
|
||||
; GISEL-NEXT: csel w0, w0, w1, ge
|
||||
; GISEL-NEXT: ret
|
||||
%c0 = fcmp olt half %v0, %v1
|
||||
%c1 = fcmp oge half %v2, %v3
|
||||
|
|
@ -1204,17 +1143,12 @@ define i32 @half_select_and_olt_one(half %v0, half %v1, half %v2, half %v3, i32
|
|||
; GISEL: ; %bb.0:
|
||||
; GISEL-NEXT: fcvt s0, h0
|
||||
; GISEL-NEXT: fcvt s1, h1
|
||||
; GISEL-NEXT: fcvt s2, h2
|
||||
; GISEL-NEXT: fcvt s3, h3
|
||||
; GISEL-NEXT: fcmp s0, s1
|
||||
; GISEL-NEXT: cset w8, mi
|
||||
; GISEL-NEXT: fcvt s0, h2
|
||||
; GISEL-NEXT: fcvt s1, h3
|
||||
; GISEL-NEXT: fcmp s0, s1
|
||||
; GISEL-NEXT: cset w9, mi
|
||||
; GISEL-NEXT: cset w10, gt
|
||||
; GISEL-NEXT: orr w9, w9, w10
|
||||
; GISEL-NEXT: and w8, w9, w8
|
||||
; GISEL-NEXT: tst w8, #0x1
|
||||
; GISEL-NEXT: csel w0, w0, w1, ne
|
||||
; GISEL-NEXT: fccmp s2, s3, #4, mi
|
||||
; GISEL-NEXT: fccmp s2, s3, #1, ne
|
||||
; GISEL-NEXT: csel w0, w0, w1, vc
|
||||
; GISEL-NEXT: ret
|
||||
%c0 = fcmp olt half %v0, %v1
|
||||
%c1 = fcmp one half %v2, %v3
|
||||
|
|
@ -1294,18 +1228,11 @@ define i32 @deep_or(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %x, i32 %y) {
|
|||
;
|
||||
; GISEL-LABEL: deep_or:
|
||||
; GISEL: ; %bb.0:
|
||||
; GISEL-NEXT: cmp w0, #0
|
||||
; GISEL-NEXT: cset w8, ne
|
||||
; GISEL-NEXT: cmp w1, #0
|
||||
; GISEL-NEXT: cset w9, ne
|
||||
; GISEL-NEXT: cmp w2, #15
|
||||
; GISEL-NEXT: cset w10, eq
|
||||
; GISEL-NEXT: mov w8, #15
|
||||
; GISEL-NEXT: cmp w2, #20
|
||||
; GISEL-NEXT: cset w11, eq
|
||||
; GISEL-NEXT: orr w10, w10, w11
|
||||
; GISEL-NEXT: and w9, w10, w9
|
||||
; GISEL-NEXT: and w8, w9, w8
|
||||
; GISEL-NEXT: tst w8, #0x1
|
||||
; GISEL-NEXT: ccmp w2, w8, #4, ne
|
||||
; GISEL-NEXT: ccmp w1, wzr, #4, eq
|
||||
; GISEL-NEXT: ccmp w0, wzr, #4, ne
|
||||
; GISEL-NEXT: csel w0, w4, w5, ne
|
||||
; GISEL-NEXT: ret
|
||||
%c0 = icmp ne i32 %a0, 0
|
||||
|
|
@ -1333,18 +1260,11 @@ define i32 @deep_or1(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %x, i32 %y) {
|
|||
;
|
||||
; GISEL-LABEL: deep_or1:
|
||||
; GISEL: ; %bb.0:
|
||||
; GISEL-NEXT: cmp w0, #0
|
||||
; GISEL-NEXT: cset w8, ne
|
||||
; GISEL-NEXT: cmp w1, #0
|
||||
; GISEL-NEXT: cset w9, ne
|
||||
; GISEL-NEXT: cmp w2, #15
|
||||
; GISEL-NEXT: cset w10, eq
|
||||
; GISEL-NEXT: mov w8, #15
|
||||
; GISEL-NEXT: cmp w2, #20
|
||||
; GISEL-NEXT: cset w11, eq
|
||||
; GISEL-NEXT: orr w10, w10, w11
|
||||
; GISEL-NEXT: and w8, w8, w10
|
||||
; GISEL-NEXT: and w8, w8, w9
|
||||
; GISEL-NEXT: tst w8, #0x1
|
||||
; GISEL-NEXT: ccmp w2, w8, #4, ne
|
||||
; GISEL-NEXT: ccmp w0, wzr, #4, eq
|
||||
; GISEL-NEXT: ccmp w1, wzr, #4, ne
|
||||
; GISEL-NEXT: csel w0, w4, w5, ne
|
||||
; GISEL-NEXT: ret
|
||||
%c0 = icmp ne i32 %a0, 0
|
||||
|
|
@ -1372,18 +1292,11 @@ define i32 @deep_or2(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %x, i32 %y) {
|
|||
;
|
||||
; GISEL-LABEL: deep_or2:
|
||||
; GISEL: ; %bb.0:
|
||||
; GISEL-NEXT: cmp w0, #0
|
||||
; GISEL-NEXT: cset w8, ne
|
||||
; GISEL-NEXT: cmp w1, #0
|
||||
; GISEL-NEXT: cset w9, ne
|
||||
; GISEL-NEXT: cmp w2, #15
|
||||
; GISEL-NEXT: cset w10, eq
|
||||
; GISEL-NEXT: mov w8, #15
|
||||
; GISEL-NEXT: cmp w2, #20
|
||||
; GISEL-NEXT: cset w11, eq
|
||||
; GISEL-NEXT: orr w10, w10, w11
|
||||
; GISEL-NEXT: and w8, w8, w9
|
||||
; GISEL-NEXT: and w8, w8, w10
|
||||
; GISEL-NEXT: tst w8, #0x1
|
||||
; GISEL-NEXT: ccmp w2, w8, #4, ne
|
||||
; GISEL-NEXT: ccmp w1, wzr, #4, eq
|
||||
; GISEL-NEXT: ccmp w0, wzr, #4, ne
|
||||
; GISEL-NEXT: csel w0, w4, w5, ne
|
||||
; GISEL-NEXT: ret
|
||||
%c0 = icmp ne i32 %a0, 0
|
||||
|
|
|
|||
Loading…
Reference in New Issue