forked from OSchip/llvm-project
AMDGPU/GlobalISel: Fix constant bus violation with source modifiers
This looked through copies to find the source modifiers, which may have been SGPR->VGPR copies added to avoid potential constant bus violations. Re-insert a copy to a VGPR if this happens.
This commit is contained in:
Matt Arsenault
Matt Arsenault
parent
5125803d34
commit
b64aa8c715
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@ -2135,8 +2135,9 @@ AMDGPUInstructionSelector::selectVCSRC(MachineOperand &Root) const {
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}
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std::pair<Register, unsigned>
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AMDGPUInstructionSelector::selectVOP3ModsImpl(
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Register Src) const {
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AMDGPUInstructionSelector::selectVOP3ModsImpl(MachineOperand &Root) const {
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Register Src = Root.getReg();
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Register OrigSrc = Src;
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unsigned Mods = 0;
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MachineInstr *MI = getDefIgnoringCopies(Src, *MRI);
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@ -2151,6 +2152,20 @@ AMDGPUInstructionSelector::selectVOP3ModsImpl(
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Mods |= SISrcMods::ABS;
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}
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if (Mods != 0 &&
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RBI.getRegBank(Src, *MRI, TRI)->getID() != AMDGPU::VGPRRegBankID) {
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MachineInstr *UseMI = Root.getParent();
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// If we looked through copies to find source modifiers on an SGPR operand,
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// we now have an SGPR register source. To avoid potentially violating the
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// constant bus restriction, we need to insert a copy to a VGPR.
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Register VGPRSrc = MRI->cloneVirtualRegister(OrigSrc);
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BuildMI(*UseMI->getParent(), UseMI, UseMI->getDebugLoc(),
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TII.get(AMDGPU::COPY), VGPRSrc)
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.addReg(Src);
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Src = VGPRSrc;
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}
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return std::make_pair(Src, Mods);
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}
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@ -2168,7 +2183,7 @@ InstructionSelector::ComplexRendererFns
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AMDGPUInstructionSelector::selectVOP3Mods0(MachineOperand &Root) const {
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Register Src;
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unsigned Mods;
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std::tie(Src, Mods) = selectVOP3ModsImpl(Root.getReg());
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std::tie(Src, Mods) = selectVOP3ModsImpl(Root);
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return {{
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[=](MachineInstrBuilder &MIB) { MIB.addReg(Src); },
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@ -2191,7 +2206,7 @@ InstructionSelector::ComplexRendererFns
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AMDGPUInstructionSelector::selectVOP3Mods(MachineOperand &Root) const {
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Register Src;
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unsigned Mods;
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std::tie(Src, Mods) = selectVOP3ModsImpl(Root.getReg());
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std::tie(Src, Mods) = selectVOP3ModsImpl(Root);
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return {{
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[=](MachineInstrBuilder &MIB) { MIB.addReg(Src); },
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@ -2215,7 +2230,7 @@ InstructionSelector::ComplexRendererFns
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AMDGPUInstructionSelector::selectVOP3Mods_nnan(MachineOperand &Root) const {
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Register Src;
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unsigned Mods;
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std::tie(Src, Mods) = selectVOP3ModsImpl(Root.getReg());
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std::tie(Src, Mods) = selectVOP3ModsImpl(Root);
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if (!TM.Options.NoNaNsFPMath && !isKnownNeverNaN(Src, *MRI))
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return None;
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@ -126,7 +126,7 @@ private:
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bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const;
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std::pair<Register, unsigned>
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selectVOP3ModsImpl(Register Src) const;
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selectVOP3ModsImpl(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectVCSRC(MachineOperand &Root) const;
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@ -228,6 +228,73 @@ define amdgpu_ps float @fcmp_s_s(float inreg %src0, float inreg %src1) {
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ret float %result
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}
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define amdgpu_ps float @select_vcc_s_s(float %cmp0, float %cmp1, float inreg %src0, float inreg %src1) {
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; GFX9-LABEL: name: select_vcc_s_s
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; GFX9: bb.1 (%ir-block.0):
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; GFX9: liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1
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; GFX9: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; GFX9: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; GFX9: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
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; GFX9: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
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; GFX9: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(oeq), [[COPY]](s32), [[COPY1]]
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; GFX9: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
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; GFX9: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY3]](s32)
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; GFX9: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[FCMP]](s1), [[COPY4]], [[COPY5]]
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; GFX9: $vgpr0 = COPY [[SELECT]](s32)
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; GFX9: SI_RETURN_TO_EPILOG implicit $vgpr0
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; GFX10-LABEL: name: select_vcc_s_s
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; GFX10: bb.1 (%ir-block.0):
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; GFX10: liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1
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; GFX10: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; GFX10: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; GFX10: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
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; GFX10: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
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; GFX10: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(oeq), [[COPY]](s32), [[COPY1]]
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; GFX10: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
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; GFX10: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY3]](s32)
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; GFX10: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[FCMP]](s1), [[COPY4]], [[COPY5]]
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; GFX10: $vgpr0 = COPY [[SELECT]](s32)
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; GFX10: SI_RETURN_TO_EPILOG implicit $vgpr0
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%cmp = fcmp oeq float %cmp0, %cmp1
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%result = select i1 %cmp, float %src0, float %src1
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ret float %result
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}
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define amdgpu_ps float @select_vcc_fneg_s_s(float %cmp0, float %cmp1, float inreg %src0, float inreg %src1) {
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; GFX9-LABEL: name: select_vcc_fneg_s_s
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; GFX9: bb.1 (%ir-block.0):
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; GFX9: liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1
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; GFX9: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; GFX9: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; GFX9: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
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; GFX9: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
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; GFX9: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(oeq), [[COPY]](s32), [[COPY1]]
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; GFX9: [[FNEG:%[0-9]+]]:sgpr(s32) = G_FNEG [[COPY2]]
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; GFX9: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[FNEG]](s32)
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; GFX9: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY3]](s32)
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; GFX9: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[FCMP]](s1), [[COPY4]], [[COPY5]]
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; GFX9: $vgpr0 = COPY [[SELECT]](s32)
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; GFX9: SI_RETURN_TO_EPILOG implicit $vgpr0
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; GFX10-LABEL: name: select_vcc_fneg_s_s
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; GFX10: bb.1 (%ir-block.0):
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; GFX10: liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1
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; GFX10: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; GFX10: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; GFX10: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
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; GFX10: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
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; GFX10: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(oeq), [[COPY]](s32), [[COPY1]]
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; GFX10: [[FNEG:%[0-9]+]]:sgpr(s32) = G_FNEG [[COPY2]]
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; GFX10: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[FNEG]](s32)
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; GFX10: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY3]](s32)
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; GFX10: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[FCMP]](s1), [[COPY4]], [[COPY5]]
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; GFX10: $vgpr0 = COPY [[SELECT]](s32)
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; GFX10: SI_RETURN_TO_EPILOG implicit $vgpr0
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%cmp = fcmp oeq float %cmp0, %cmp1
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%neg.src0 = fneg float %src0
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%result = select i1 %cmp, float %neg.src0, float %src1
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ret float %result
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}
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; Constant bus used by vcc
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define amdgpu_ps float @amdgcn_div_fmas_sss(float inreg %src, float %cmp.src) {
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; GFX9-LABEL: name: amdgcn_div_fmas_sss
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@ -165,7 +165,8 @@ body: |
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; GFX6-LABEL: name: fadd_s32_fneg_copy_sgpr
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; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 1, [[COPY1]], 0, 0, implicit $exec
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; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
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; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 1, [[COPY2]], 0, 0, implicit $exec
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; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr(s32) = COPY $sgpr0
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@ -202,3 +203,90 @@ body: |
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S_ENDPGM 0, implicit %6
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...
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# The source modifier lookup searches through SGPR->VGPR copies. Make
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# sure we don't violate the constant bus restriction when we look at
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# the source.
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---
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name: fadd_s32_copy_fabs_sgpr_copy_fabs_sgpr
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; GFX6-LABEL: name: fadd_s32_copy_fabs_sgpr_copy_fabs_sgpr
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; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
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; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
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; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 2, [[COPY2]], 2, [[COPY3]], 0, 0, implicit $exec
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; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = COPY $sgpr1
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%2:sgpr(s32) = G_FABS %0
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%3:sgpr(s32) = G_FABS %1
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%4:vgpr(s32) = COPY %2
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%5:vgpr(s32) = COPY %3
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%6:vgpr(s32) = G_FADD %4, %5
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S_ENDPGM 0, implicit %6
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...
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---
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name: fadd_s32_copy_fneg_sgpr_copy_fneg_sgpr
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; GFX6-LABEL: name: fadd_s32_copy_fneg_sgpr_copy_fneg_sgpr
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; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
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; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
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; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 1, [[COPY2]], 1, [[COPY3]], 0, 0, implicit $exec
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; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = COPY $sgpr1
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%2:sgpr(s32) = G_FNEG %0
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%3:sgpr(s32) = G_FNEG %1
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%4:vgpr(s32) = COPY %2
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%5:vgpr(s32) = COPY %3
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%6:vgpr(s32) = G_FADD %4, %5
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S_ENDPGM 0, implicit %6
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...
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---
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name: fadd_s32_copy_fneg_fabs_sgpr_copy_fneg_fabs_sgpr
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; GFX6-LABEL: name: fadd_s32_copy_fneg_fabs_sgpr_copy_fneg_fabs_sgpr
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; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
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; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
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; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 3, [[COPY2]], 3, [[COPY3]], 0, 0, implicit $exec
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; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = COPY $sgpr1
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%2:sgpr(s32) = G_FABS %0
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%3:sgpr(s32) = G_FABS %1
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%4:sgpr(s32) = G_FNEG %2
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%5:sgpr(s32) = G_FNEG %3
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%6:vgpr(s32) = COPY %4
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%7:vgpr(s32) = COPY %5
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%8:vgpr(s32) = G_FADD %6, %7
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S_ENDPGM 0, implicit %8
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...
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@ -166,7 +166,8 @@ body: |
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; GFX6-LABEL: name: fadd_s64_fneg_copy_sgpr
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; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; GFX6: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 1, [[COPY1]], 0, 0, implicit $exec
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; GFX6: [[COPY2:%[0-9]+]]:vreg_64 = COPY [[COPY1]]
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; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 1, [[COPY2]], 0, 0, implicit $exec
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; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]
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%0:vgpr(s64) = COPY $vgpr0_vgpr1
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%1:sgpr(s64) = COPY $sgpr0_sgpr1
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@ -176,3 +177,90 @@ body: |
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S_ENDPGM 0, implicit %4
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...
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# The source modifier lookup searches through SGPR->VGPR copies. Make
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# sure we don't violate the constant bus restriction when we look at
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# the source.
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---
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name: fadd_s64_copy_fabs_sgpr_copy_fabs_sgpr
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
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; GFX6-LABEL: name: fadd_s64_copy_fabs_sgpr_copy_fabs_sgpr
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; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; GFX6: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
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; GFX6: [[COPY2:%[0-9]+]]:vreg_64 = COPY [[COPY]]
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; GFX6: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[COPY1]]
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; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 2, [[COPY2]], 2, [[COPY3]], 0, 0, implicit $exec
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; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]
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%0:sgpr(s64) = COPY $sgpr0_sgpr1
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%1:sgpr(s64) = COPY $sgpr2_sgpr3
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%2:sgpr(s64) = G_FABS %0
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%3:sgpr(s64) = G_FABS %1
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%4:vgpr(s64) = COPY %2
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%5:vgpr(s64) = COPY %3
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%6:vgpr(s64) = G_FADD %4, %5
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S_ENDPGM 0, implicit %6
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...
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---
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name: fadd_s64_copy_fneg_sgpr_copy_fneg_sgpr
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; GFX6-LABEL: name: fadd_s64_copy_fneg_sgpr_copy_fneg_sgpr
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; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; GFX6: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
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; GFX6: [[COPY2:%[0-9]+]]:vreg_64 = COPY [[COPY]]
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; GFX6: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[COPY1]]
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; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 1, [[COPY2]], 1, [[COPY3]], 0, 0, implicit $exec
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; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]
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%0:sgpr(s64) = COPY $sgpr0_sgpr1
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%1:sgpr(s64) = COPY $sgpr2_sgpr3
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%2:sgpr(s64) = G_FNEG %0
|
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%3:sgpr(s64) = G_FNEG %1
|
||||
%4:vgpr(s64) = COPY %2
|
||||
%5:vgpr(s64) = COPY %3
|
||||
%6:vgpr(s64) = G_FADD %4, %5
|
||||
S_ENDPGM 0, implicit %6
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
name: fadd_s64_copy_fneg_fabs_sgpr_copy_fneg_fabs_sgpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0, $sgpr1
|
||||
; GFX6-LABEL: name: fadd_s64_copy_fneg_fabs_sgpr_copy_fneg_fabs_sgpr
|
||||
; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
||||
; GFX6: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
|
||||
; GFX6: [[COPY2:%[0-9]+]]:vreg_64 = COPY [[COPY]]
|
||||
; GFX6: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[COPY1]]
|
||||
; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 3, [[COPY2]], 3, [[COPY3]], 0, 0, implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]
|
||||
%0:sgpr(s64) = COPY $sgpr0_sgpr1
|
||||
%1:sgpr(s64) = COPY $sgpr2_sgpr3
|
||||
%2:sgpr(s64) = G_FABS %0
|
||||
%3:sgpr(s64) = G_FABS %1
|
||||
%4:sgpr(s64) = G_FNEG %2
|
||||
%5:sgpr(s64) = G_FNEG %3
|
||||
%6:vgpr(s64) = COPY %4
|
||||
%7:vgpr(s64) = COPY %5
|
||||
%8:vgpr(s64) = G_FADD %6, %7
|
||||
S_ENDPGM 0, implicit %8
|
||||
|
||||
...
|
||||
|
|
|
|||
Loading…
Reference in New Issue