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Add pattern for OR 

llvm-svn: 70720
This commit is contained in:
Anton Korobeynikov 2009-05-03 13:05:00 +00:00
parent 654cb0a761
commit b638fb10f5
3 changed files with 11 additions and 2 deletions
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1
llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
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@ -54,7 +54,6 @@ MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
setShiftAmountType(MVT::i8);
setOperationAction(ISD::SRA, MVT::i16, Custom);
setOperationAction(ISD::RET, MVT::Other, Custom);
}

1
llvm/lib/Target/MSP430/MSP430ISelLowering.h
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@ -50,7 +50,6 @@ namespace llvm {
SDValue LowerRET(SDValue Op, SelectionDAG &DAG);
SDValue LowerCCCArguments(SDValue Op, SelectionDAG &DAG);
SDValue LowerShifts(SDValue Op, SelectionDAG &DAG);
private:
const MSP430Subtarget &Subtarget;
const MSP430TargetMachine &TM;

11
llvm/lib/Target/MSP430/MSP430InstrInfo.td
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@ -152,4 +152,15 @@ def SAR16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
[(set GR16:$dst, (MSP430rra GR16:$src)),
(implicit SR)]>;
} // Defs = [SR]
let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y
def OR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
"bis.w\t{$src2, $dst|$dst, $src2}",
[(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>;
}
def OR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
"bis.w\t{$src2, $dst|$dst, $src2}",
[(set GR16:$dst, (or GR16:$src1, imm:$src2))]>;
} // isTwoAddress = 1