Add a -regalloc=default option that chooses a register allocator based on the -O

optimization level.

This only really affects llc for now because both the llvm-gcc and clang front
ends override the default register allocator. I intend to remove that code later.

llvm-svn: 104904

llvm/include/llvm/CodeGen/Passes.h

@@ -85,9 +85,10 @@ namespace llvm {
   ///
   FunctionPass *createDeadMachineInstructionElimPass();
 
-  /// Creates a register allocator as the user specified on the command line.
+  /// Creates a register allocator as the user specified on the command line, or
+  /// picks one that matches OptLevel.
   ///
-  FunctionPass *createRegisterAllocator();
+  FunctionPass *createRegisterAllocator(CodeGenOpt::Level OptLevel);
 
   /// LocalRegisterAllocation Pass - This pass register allocates the input code
   /// a basic block at a time, yielding code better than the simple register

llvm/lib/CodeGen/LLVMTargetMachine.cpp

@@ -358,7 +358,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
                    /* allowDoubleDefs= */ true);
 
   // Perform register allocation.
-  PM.add(createRegisterAllocator());
+  PM.add(createRegisterAllocator(OptLevel));
   printAndVerify(PM, "After Register Allocation");
 
   // Perform stack slot coloring and post-ra machine LICM.

llvm/lib/CodeGen/Passes.cpp

@@ -24,6 +24,11 @@ using namespace llvm;
 //===---------------------------------------------------------------------===//
 MachinePassRegistry RegisterRegAlloc::Registry;
 
+static FunctionPass *createDefaultRegisterAllocator() { return 0; }
+static RegisterRegAlloc
+defaultRegAlloc("default",
+                "pick register allocator based on -O option",
+                createDefaultRegisterAllocator);
 
 //===---------------------------------------------------------------------===//
 ///
@@ -33,8 +38,8 @@ MachinePassRegistry RegisterRegAlloc::Registry;
 static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
                RegisterPassParser<RegisterRegAlloc> >
 RegAlloc("regalloc",
-         cl::init(&createLinearScanRegisterAllocator),
+         cl::init(&createDefaultRegisterAllocator),
-         cl::desc("Register allocator to use (default=linearscan)")); 
+         cl::desc("Register allocator to use"));
 
 
 //===---------------------------------------------------------------------===//
@@ -42,7 +47,7 @@ RegAlloc("regalloc",
 /// createRegisterAllocator - choose the appropriate register allocator.
 ///
 //===---------------------------------------------------------------------===//
-FunctionPass *llvm::createRegisterAllocator() {
+FunctionPass *llvm::createRegisterAllocator(CodeGenOpt::Level OptLevel) {
   RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
 
   if (!Ctor) {
@@ -50,5 +55,14 @@ FunctionPass *llvm::createRegisterAllocator() {
     RegisterRegAlloc::setDefault(RegAlloc);
   }
 
-  return Ctor();
+  if (Ctor != createDefaultRegisterAllocator)
+    return Ctor();
+
+  // When the 'default' allocator is requested, pick one based on OptLevel.
+  switch (OptLevel) {
+  case CodeGenOpt::None:
+    return createLocalRegisterAllocator();
+  default:
+    return createLinearScanRegisterAllocator();
+  }
 }

llvm/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll

@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm -mattr=+neon -O0
+; RUN: llc < %s -march=arm -mattr=+neon -O0 -regalloc=linearscan
 
 ; This test would crash the rewriter when trying to handle a spill after one of
 ; the @llvm.arm.neon.vld3.v8i8 defined three parts of a register.

llvm/test/CodeGen/X86/2008-05-21-CoalescerBug.ll

@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -O0 -fast-isel=false | grep mov | count 5
+; RUN: llc < %s -march=x86 -O0 -fast-isel=false -regalloc=linearscan | grep mov | count 5
 ; PR2343
 
 	%llvm.dbg.anchor.type = type { i32, i32 }

llvm/test/CodeGen/X86/fast-isel-bc.ll

@@ -1,4 +1,4 @@
-; RUN: llc < %s -O0 -march=x86-64 -mattr=+mmx | FileCheck %s
+; RUN: llc < %s -O0 -regalloc=linearscan -march=x86-64 -mattr=+mmx | FileCheck %s
 ; PR4684
 
 target datalayout =

llvm/test/CodeGen/X86/inline-asm-tied.ll

@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin9 -O0 | grep {movl	%edx, 12(%esp)} | count 2
+; RUN: llc < %s -mtriple=i386-apple-darwin9 -O0 -regalloc=linearscan | grep {movl	%edx, 12(%esp)} | count 2
 ; rdar://6992609
 
 target triple = "i386-apple-darwin9.0"