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[VE] Support floating-point arithmetic instructions in MC layer 

Summary:
Add regression tests of asmparser, mccodeemitter, and disassembler for
floating-point arithmetic instructions.  Add FADDQ, FSUBQ, FMULQ, and
FCMPQ instructions and F128 register class too.

Differential Revision: https://reviews.llvm.org/D81386
This commit is contained in:
Kazushi (Jam) Marukawa 2020-06-08 15:58:31 +02:00 committed by Simon Moll
parent 731fee8b42
commit b60404a666
10 changed files with 200 additions and 0 deletions
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19
llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
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@ -111,6 +111,12 @@ static const MCPhysReg F32Regs[64] = {
VE::SF56, VE::SF57, VE::SF58, VE::SF59, VE::SF60, VE::SF61, VE::SF62,
VE::SF63};
static const MCPhysReg F128Regs[32] = {
VE::Q0, VE::Q1, VE::Q2, VE::Q3, VE::Q4, VE::Q5, VE::Q6, VE::Q7,
VE::Q8, VE::Q9, VE::Q10, VE::Q11, VE::Q12, VE::Q13, VE::Q14, VE::Q15,
VE::Q16, VE::Q17, VE::Q18, VE::Q19, VE::Q20, VE::Q21, VE::Q22, VE::Q23,
VE::Q24, VE::Q25, VE::Q26, VE::Q27, VE::Q28, VE::Q29, VE::Q30, VE::Q31};
static const MCPhysReg MISCRegs[31] = {
VE::USRCC, VE::PSW, VE::SAR, VE::NoRegister,
VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::PMMR,
@ -549,6 +555,15 @@ public:
return true;
}
static bool MorphToF128Reg(VEOperand &Op) {
unsigned Reg = Op.getReg();
unsigned regIdx = Reg - VE::SX0;
if (regIdx % 2 || regIdx > 63)
return false;
Op.Reg.RegNum = F128Regs[regIdx / 2];
return true;
}
static bool MorphToMISCReg(VEOperand &Op) {
const auto *ConstExpr = dyn_cast<MCConstantExpr>(Op.getImm());
if (!ConstExpr)
@ -1163,6 +1178,10 @@ unsigned VEAsmParser::validateTargetOperandClass(MCParsedAsmOperand &GOp,
if (Op.isReg() && VEOperand::MorphToI32Reg(Op))
return MCTargetAsmParser::Match_Success;
break;
case MCK_F128:
if (Op.isReg() && VEOperand::MorphToF128Reg(Op))
return MCTargetAsmParser::Match_Success;
break;
case MCK_MISC:
if (Op.isImm() && VEOperand::MorphToMISCReg(Op))
return MCTargetAsmParser::Match_Success;

16
llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp
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@ -89,6 +89,12 @@ static const unsigned F32RegDecoderTable[] = {
VE::SF56, VE::SF57, VE::SF58, VE::SF59, VE::SF60, VE::SF61, VE::SF62,
VE::SF63};
static const unsigned F128RegDecoderTable[] = {
VE::Q0, VE::Q1, VE::Q2, VE::Q3, VE::Q4, VE::Q5, VE::Q6, VE::Q7,
VE::Q8, VE::Q9, VE::Q10, VE::Q11, VE::Q12, VE::Q13, VE::Q14, VE::Q15,
VE::Q16, VE::Q17, VE::Q18, VE::Q19, VE::Q20, VE::Q21, VE::Q22, VE::Q23,
VE::Q24, VE::Q25, VE::Q26, VE::Q27, VE::Q28, VE::Q29, VE::Q30, VE::Q31};
static const unsigned MiscRegDecoderTable[] = {
VE::USRCC, VE::PSW, VE::SAR, VE::NoRegister,
VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::PMMR,
@ -129,6 +135,16 @@ static DecodeStatus DecodeF32RegisterClass(MCInst &Inst, unsigned RegNo,
return MCDisassembler::Success;
}
static DecodeStatus DecodeF128RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder) {
if (RegNo % 2 || RegNo > 63)
return MCDisassembler::Fail;
unsigned Reg = F128RegDecoderTable[RegNo / 2];
Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
static DecodeStatus DecodeMISCRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder) {

11
llvm/lib/Target/VE/VEInstrInfo.td
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@ -177,12 +177,14 @@ def mimm : Operand<i32>, PatLeaf<(imm), [{
def simm7fp : Operand<i32>, PatLeaf<(fpimm), [{
return isInt<7>(getFpImmVal(N));
}], LO7FP> {
let ParserMatchClass = SImm7AsmOperand;
let DecoderMethod = "DecodeSIMM7";
}
// mimmfp - Special fp immediate value of sequential bit stream of 0 or 1.
def mimmfp : Operand<i32>, PatLeaf<(fpimm), [{
return isMImmVal(getFpImmVal(N)); }], MIMMFP> {
let ParserMatchClass = MImmAsmOperand;
let PrintMethod = "printMImmOperand";
}
@ -190,6 +192,7 @@ def mimmfp : Operand<i32>, PatLeaf<(fpimm), [{
// Float value places at higher bits, so ignore lower 32 bits.
def mimmfp32 : Operand<i32>, PatLeaf<(fpimm), [{
return isMImm32Val(getFpImmVal(N) >> 32); }], MIMMFP> {
let ParserMatchClass = MImmAsmOperand;
let PrintMethod = "printMImmOperand";
}
@ -1127,9 +1130,17 @@ let cw = 1, cx = 1 in
defm FMINS : RRFm<"fmin.s", 0x3E, F32, f32, fminnum, simm7fp, mimmfp32>;
// Section 8.7.7 - FAQ (Floating Add Quadruple)
defm FADDQ : RRFm<"fadd.q", 0x6C, F128, f128>;
// Section 8.7.8 - FSQ (Floating Subtract Quadruple)
defm FSUBQ : RRFm<"fsub.q", 0x7C, F128, f128>;
// Section 8.7.9 - FMQ (Floating Subtract Quadruple)
defm FMULQ : RRFm<"fmul.q", 0x6D, F128, f128>;
// Section 8.7.10 - FCQ (Floating Compare Quadruple)
defm FCMPQ : RRNCbm<"fcmp.q", 0x7D, I64, f64, F128, f128, null_frag, simm7fp,
mimmfp>;
// Section 8.7.11 - FIX (Convert to Fixed Point)
// cx: double/float, cw: sx/zx, sz{0-3} = round

18
llvm/lib/Target/VE/VERegisterInfo.td
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@ -31,6 +31,8 @@ let Namespace = "VE" in {
def sub_i16 : SubRegIndex<16, 48>; // Low 16 bit (48..63)
def sub_i32 : SubRegIndex<32, 32>; // Low 32 bit (32..63)
def sub_f32 : SubRegIndex<32>; // High 32 bit (0..31)
def sub_even : SubRegIndex<64>; // High 64 bit (0..63)
def sub_odd : SubRegIndex<64, 64>; // Low 64 bit (64..127)
def AsmName : RegAltNameIndex;
}
@ -98,6 +100,18 @@ foreach I = 0-63 in
def SX#I : VEReg<I, "s"#I, [!cast<VEReg>("SW"#I), !cast<VEReg>("SF"#I)],
["s"#I]>, DwarfRegNum<[I]>;
// Aliases of the S* registers used to hold 128-bit for values (long doubles).
// Following foreach represents something like:
// def Q0 : VEReg<0, "q0", [SX0, SX1], ["s0"]>;
// def Q1 : VEReg<2, "q2", [SX2, SX3], ["s2"]>;
// ...
let SubRegIndices = [sub_even, sub_odd], CoveredBySubRegs = 1 in
foreach I = 0-31 in
def Q#I : VEReg<!shl(I,1), "q"#I,
[!cast<VEReg>("SX"#!shl(I,1)),
!cast<VEReg>("SX"#!add(!shl(I,1),1))],
["s"#!shl(I,1)]>;
} // RegAltNameIndices = [AsmName]
// Register classes.
@ -124,3 +138,7 @@ def F32 : RegisterClass<"VE", [f32], 32,
(add (sequence "SF%u", 0, 7),
(sequence "SF%u", 34, 63),
(sequence "SF%u", 8, 33))>;
def F128 : RegisterClass<"VE", [f128], 128,
(add (sequence "Q%u", 0, 3),
(sequence "Q%u", 17, 31),
(sequence "Q%u", 4, 16))>;

24
llvm/test/MC/VE/FADD.s Normal file
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@ -0,0 +1,24 @@
# RUN: llvm-mc -triple=ve --show-encoding < %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
# RUN: | FileCheck %s --check-prefixes=CHECK-INST
# CHECK-INST: fadd.d %s11, %s20, %s22
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x94,0x0b,0x4c]
fadd.d %s11, %s20, %s22
# CHECK-INST: fadd.s %s11, 22, %s22
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x16,0x8b,0x4c]
fadd.s %s11, 22, %s22
# CHECK-INST: fadd.d %s11, 63, (60)1
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x3c,0x3f,0x0b,0x4c]
fadd.d %s11, 63, (60)1
# CHECK-INST: fadd.s %s11, -64, (22)0
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x56,0x40,0x8b,0x4c]
fadd.s %s11, -64, (22)0
# CHECK-INST: fadd.q %s12, %s20, %s22
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x94,0x0c,0x6c]
fadd.q %s12, %s20, %s22

24
llvm/test/MC/VE/FCMP.s Normal file
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@ -0,0 +1,24 @@
# RUN: llvm-mc -triple=ve --show-encoding < %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
# RUN: | FileCheck %s --check-prefixes=CHECK-INST
# CHECK-INST: fcmp.d %s11, %s20, %s22
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x94,0x0b,0x7e]
fcmp.d %s11, %s20, %s22
# CHECK-INST: fcmp.s %s11, 22, %s22
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x16,0x8b,0x7e]
fcmp.s %s11, 22, %s22
# CHECK-INST: fcmp.d %s11, 63, (60)1
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x3c,0x3f,0x0b,0x7e]
fcmp.d %s11, 63, (60)1
# CHECK-INST: fcmp.s %s11, -64, (22)0
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x56,0x40,0x8b,0x7e]
fcmp.s %s11, -64, (22)0
# CHECK-INST: fcmp.q %s11, %s20, %s22
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x94,0x0b,0x7d]
fcmp.q %s11, %s20, %s22

20
llvm/test/MC/VE/FDIV.s Normal file
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@ -0,0 +1,20 @@
# RUN: llvm-mc -triple=ve --show-encoding < %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
# RUN: | FileCheck %s --check-prefixes=CHECK-INST
# CHECK-INST: fdiv.d %s11, %s20, %s22
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x94,0x0b,0x5d]
fdiv.d %s11, %s20, %s22
# CHECK-INST: fdiv.s %s11, 22, %s22
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x16,0x8b,0x5d]
fdiv.s %s11, 22, %s22
# CHECK-INST: fdiv.d %s11, 63, (60)1
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x3c,0x3f,0x0b,0x5d]
fdiv.d %s11, 63, (60)1
# CHECK-INST: fdiv.s %s11, -64, (22)0
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x56,0x40,0x8b,0x5d]
fdiv.s %s11, -64, (22)0

20
llvm/test/MC/VE/FMAXMIN.s Normal file
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@ -0,0 +1,20 @@
# RUN: llvm-mc -triple=ve --show-encoding < %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
# RUN: | FileCheck %s --check-prefixes=CHECK-INST
# CHECK-INST: fmax.d %s11, %s20, %s22
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x94,0x0b,0x3e]
fmax.d %s11, %s20, %s22
# CHECK-INST: fmax.s %s11, 22, %s22
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x16,0x8b,0x3e]
fmax.s %s11, 22, %s22
# CHECK-INST: fmin.d %s11, 63, (63)1
# CHECK-ENCODING: encoding: [0x80,0x00,0x00,0x00,0x3f,0x3f,0x0b,0x3e]
fmin.d %s11, 63, (63)1
# CHECK-INST: fmin.s %s11, -64, %s22
# CHECK-ENCODING: encoding: [0x80,0x00,0x00,0x00,0x96,0x40,0x8b,0x3e]
fmin.s %s11, -64, %s22

24
llvm/test/MC/VE/FMUL.s Normal file
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@ -0,0 +1,24 @@
# RUN: llvm-mc -triple=ve --show-encoding < %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
# RUN: | FileCheck %s --check-prefixes=CHECK-INST
# CHECK-INST: fmul.d %s11, %s20, %s22
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x94,0x0b,0x4d]
fmul.d %s11, %s20, %s22
# CHECK-INST: fmul.s %s11, 22, %s22
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x16,0x8b,0x4d]
fmul.s %s11, 22, %s22
# CHECK-INST: fmul.d %s11, 63, (60)1
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x3c,0x3f,0x0b,0x4d]
fmul.d %s11, 63, (60)1
# CHECK-INST: fmul.s %s11, -64, (22)0
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x56,0x40,0x8b,0x4d]
fmul.s %s11, -64, (22)0
# CHECK-INST: fmul.q %s12, %s20, %s22
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x94,0x0c,0x6d]
fmul.q %s12, %s20, %s22

24
llvm/test/MC/VE/FSUB.s Normal file
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@ -0,0 +1,24 @@
# RUN: llvm-mc -triple=ve --show-encoding < %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
# RUN: | FileCheck %s --check-prefixes=CHECK-INST
# CHECK-INST: fsub.d %s11, %s20, %s22
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x94,0x0b,0x5c]
fsub.d %s11, %s20, %s22
# CHECK-INST: fsub.s %s11, 22, %s22
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x16,0x8b,0x5c]
fsub.s %s11, 22, %s22
# CHECK-INST: fsub.d %s11, 63, (60)1
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x3c,0x3f,0x0b,0x5c]
fsub.d %s11, 63, (60)1
# CHECK-INST: fsub.s %s11, -64, (22)0
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x56,0x40,0x8b,0x5c]
fsub.s %s11, -64, (22)0
# CHECK-INST: fsub.q %s12, %s20, %s22
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x94,0x0c,0x7c]
fsub.q %s12, %s20, %s22