forked from OSchip/llvm-project
parent
6151654c00
commit
b5f61bdeeb
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@ -131,7 +131,7 @@ private:
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/// one element in @p Targets.
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/// one element in @p Targets.
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MemoryAccess *hasWriteBetween(ScopStmt *Stmt, MemoryAccess *From,
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MemoryAccess *hasWriteBetween(ScopStmt *Stmt, MemoryAccess *From,
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MemoryAccess *To, isl::map Targets) {
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MemoryAccess *To, isl::map Targets) {
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auto TargetsSpace = give(isl_map_get_space(Targets.keep()));
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auto TargetsSpace = Targets.get_space();
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bool Started = Stmt->isRegionStmt();
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bool Started = Stmt->isRegionStmt();
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for (auto *Acc : *Stmt) {
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for (auto *Acc : *Stmt) {
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@ -154,18 +154,16 @@ private:
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continue;
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continue;
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auto AccRel = give(Acc->getAccessRelation());
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auto AccRel = give(Acc->getAccessRelation());
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auto AccRelSpace = give(isl_map_get_space(AccRel.keep()));
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auto AccRelSpace = AccRel.get_space();
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// Spaces being different means that they access different arrays.
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// Spaces being different means that they access different arrays.
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if (isl_space_has_equal_tuples(TargetsSpace.keep(), AccRelSpace.keep()) ==
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if (!TargetsSpace.has_equal_tuples(AccRelSpace))
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isl_bool_false)
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continue;
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continue;
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AccRel = give(isl_map_intersect_domain(AccRel.take(),
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AccRel = AccRel.intersect_domain(give(Acc->getStatement()->getDomain()));
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Acc->getStatement()->getDomain()));
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AccRel = AccRel.intersect_params(give(S->getContext()));
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AccRel = give(isl_map_intersect_params(AccRel.take(), S->getContext()));
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auto CommonElt = Targets.intersect(AccRel);
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auto CommonElt = give(isl_map_intersect(Targets.copy(), AccRel.copy()));
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if (!CommonElt.is_empty())
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if (isl_map_is_empty(CommonElt.keep()) != isl_bool_true)
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return Acc;
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return Acc;
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}
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}
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assert(Stmt->isRegionStmt() &&
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assert(Stmt->isRegionStmt() &&
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@ -208,9 +206,7 @@ private:
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// If all of a write's elements are overwritten, remove it.
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// If all of a write's elements are overwritten, remove it.
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isl::union_map AccRelUnion = AccRel;
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isl::union_map AccRelUnion = AccRel;
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if (isl_union_map_is_subset(AccRelUnion.keep(),
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if (AccRelUnion.is_subset(WillBeOverwritten)) {
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WillBeOverwritten.keep()) ==
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isl_bool_true) {
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DEBUG(dbgs() << "Removing " << MA
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DEBUG(dbgs() << "Removing " << MA
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<< " which will be overwritten anyway\n");
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<< " which will be overwritten anyway\n");
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@ -252,15 +248,13 @@ private:
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continue;
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continue;
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auto WARel = give(WA->getLatestAccessRelation());
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auto WARel = give(WA->getLatestAccessRelation());
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WARel = give(isl_map_intersect_domain(WARel.take(),
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WARel = WARel.intersect_domain(give(WA->getStatement()->getDomain()));
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WA->getStatement()->getDomain()));
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WARel = WARel.intersect_params(give(S->getContext()));
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WARel = give(isl_map_intersect_params(WARel.take(), S->getContext()));
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auto RARel = give(RA->getLatestAccessRelation());
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auto RARel = give(RA->getLatestAccessRelation());
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RARel = give(isl_map_intersect_domain(RARel.take(),
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RARel = RARel.intersect_domain(give(RA->getStatement()->getDomain()));
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RA->getStatement()->getDomain()));
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RARel = RARel.intersect_params(give(S->getContext()));
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RARel = give(isl_map_intersect_params(RARel.take(), S->getContext()));
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if (isl_map_is_equal(RARel.keep(), WARel.keep()) != isl_bool_true) {
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if (!RARel.is_equal(WARel)) {
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PairUnequalAccRels++;
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PairUnequalAccRels++;
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DEBUG(dbgs() << "Not cleaning up " << WA
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DEBUG(dbgs() << "Not cleaning up " << WA
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<< " because of unequal access relations:\n");
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<< " because of unequal access relations:\n");
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