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[AArch64][GlobalISel] Add selection support for <8 x s16> G_INSERT_VECTOR_ELT with GPR scalar. 

Fixes the neon intrinsics test in the test suite.
This commit is contained in:
Amara Emerson 2020-09-25 09:49:27 -07:00
parent 62c372770d
commit b5e87c9ef2
2 changed files with 30 additions and 1 deletions
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5
llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
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@ -3799,7 +3799,10 @@ static std::pair<unsigned, unsigned>
getInsertVecEltOpInfo(const RegisterBank &RB, unsigned EltSize) {
unsigned Opc, SubregIdx;
if (RB.getID() == AArch64::GPRRegBankID) {
if (EltSize == 32) {
if (EltSize == 16) {
Opc = AArch64::INSvi16gpr;
SubregIdx = AArch64::ssub;
} else if (EltSize == 32) {
Opc = AArch64::INSvi32gpr;
SubregIdx = AArch64::ssub;
} else if (EltSize == 64) {

26
llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir
View File

@ -1,6 +1,32 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=instruction-select %s -o - | FileCheck %s
---
name: v8s16_gpr
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $q1, $w0
; CHECK-LABEL: name: v8s16_gpr
; CHECK: liveins: $q1, $w0
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[INSvi16gpr:%[0-9]+]]:fpr128 = INSvi16gpr [[COPY1]], 1, [[COPY]]
; CHECK: $q0 = COPY [[INSvi16gpr]]
; CHECK: RET_ReallyLR implicit $q0
%0:gpr(s32) = COPY $w0
%trunc:gpr(s16) = G_TRUNC %0
%1:fpr(<8 x s16>) = COPY $q1
%3:gpr(s32) = G_CONSTANT i32 1
%2:fpr(<8 x s16>) = G_INSERT_VECTOR_ELT %1, %trunc:gpr(s16), %3:gpr(s32)
$q0 = COPY %2(<8 x s16>)
RET_ReallyLR implicit $q0
...
---
name: v8s16_fpr
alignment: 4
legalized: true