forked from OSchip/llvm-project
Remove FMA3 intrinsic instructions in favor of patterns.
llvm-svn: 162194
This commit is contained in:
Craig Topper
parent
37eca54912
commit
b58eec4eaf
|
|
@ -42,15 +42,7 @@ let neverHasSideEffects = 1 in {
|
|||
// Intrinsic for 213 pattern
|
||||
multiclass fma3p_rm_int<bits<8> opc, string OpcodeStr,
|
||||
PatFrag MemFrag128, PatFrag MemFrag256,
|
||||
Intrinsic Int128, Intrinsic Int256, SDNode Op213,
|
||||
ValueType OpVT128, ValueType OpVT256> {
|
||||
def r_Int : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
|
||||
(ins VR128:$src1, VR128:$src2, VR128:$src3),
|
||||
!strconcat(OpcodeStr,
|
||||
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
|
||||
[(set VR128:$dst, (Int128 VR128:$src2, VR128:$src1,
|
||||
VR128:$src3))]>;
|
||||
|
||||
SDNode Op213, ValueType OpVT128, ValueType OpVT256> {
|
||||
def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
|
||||
(ins VR128:$src1, VR128:$src2, VR128:$src3),
|
||||
!strconcat(OpcodeStr,
|
||||
|
|
@ -58,13 +50,6 @@ multiclass fma3p_rm_int<bits<8> opc, string OpcodeStr,
|
|||
[(set VR128:$dst, (OpVT128 (Op213 VR128:$src2,
|
||||
VR128:$src1, VR128:$src3)))]>;
|
||||
|
||||
def m_Int : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
|
||||
(ins VR128:$src1, VR128:$src2, f128mem:$src3),
|
||||
!strconcat(OpcodeStr,
|
||||
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
|
||||
[(set VR128:$dst, (Int128 VR128:$src2, VR128:$src1,
|
||||
(MemFrag128 addr:$src3)))]>;
|
||||
|
||||
def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
|
||||
(ins VR128:$src1, VR128:$src2, f128mem:$src3),
|
||||
!strconcat(OpcodeStr,
|
||||
|
|
@ -72,14 +57,6 @@ multiclass fma3p_rm_int<bits<8> opc, string OpcodeStr,
|
|||
[(set VR128:$dst, (OpVT128 (Op213 VR128:$src2, VR128:$src1,
|
||||
(MemFrag128 addr:$src3))))]>;
|
||||
|
||||
|
||||
def rY_Int : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
|
||||
(ins VR256:$src1, VR256:$src2, VR256:$src3),
|
||||
!strconcat(OpcodeStr,
|
||||
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
|
||||
[(set VR256:$dst, (Int256 VR256:$src2, VR256:$src1,
|
||||
VR256:$src3))]>;
|
||||
|
||||
def rY : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
|
||||
(ins VR256:$src1, VR256:$src2, VR256:$src3),
|
||||
!strconcat(OpcodeStr,
|
||||
|
|
@ -87,13 +64,6 @@ multiclass fma3p_rm_int<bits<8> opc, string OpcodeStr,
|
|||
[(set VR256:$dst, (OpVT256 (Op213 VR256:$src2, VR256:$src1,
|
||||
VR256:$src3)))]>;
|
||||
|
||||
def mY_Int : FMA3<opc, MRMSrcMem, (outs VR256:$dst),
|
||||
(ins VR256:$src1, VR256:$src2, f256mem:$src3),
|
||||
!strconcat(OpcodeStr,
|
||||
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
|
||||
[(set VR256:$dst, (Int256 VR256:$src2, VR256:$src1,
|
||||
(MemFrag256 addr:$src3)))]>;
|
||||
|
||||
def mY : FMA3<opc, MRMSrcMem, (outs VR256:$dst),
|
||||
(ins VR256:$src1, VR256:$src2, f256mem:$src3),
|
||||
!strconcat(OpcodeStr,
|
||||
|
|
@ -107,11 +77,10 @@ multiclass fma3p_rm_int<bits<8> opc, string OpcodeStr,
|
|||
multiclass fma3p_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
|
||||
string OpcodeStr, string PackTy,
|
||||
PatFrag MemFrag128, PatFrag MemFrag256,
|
||||
Intrinsic Int128, Intrinsic Int256, SDNode Op,
|
||||
ValueType OpTy128, ValueType OpTy256> {
|
||||
SDNode Op, ValueType OpTy128, ValueType OpTy256> {
|
||||
defm r213 : fma3p_rm_int <opc213, !strconcat(OpcodeStr,
|
||||
!strconcat("213", PackTy)), MemFrag128, MemFrag256,
|
||||
Int128, Int256, Op, OpTy128, OpTy256>;
|
||||
Op, OpTy128, OpTy256>;
|
||||
defm r132 : fma3p_rm <opc132,
|
||||
!strconcat(OpcodeStr, !strconcat("132", PackTy))>;
|
||||
defm r231 : fma3p_rm <opc231,
|
||||
|
|
@ -121,69 +90,176 @@ multiclass fma3p_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
|
|||
// Fused Multiply-Add
|
||||
let ExeDomain = SSEPackedSingle in {
|
||||
defm VFMADDPS : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "ps", memopv4f32,
|
||||
memopv8f32, int_x86_fma_vfmadd_ps,
|
||||
int_x86_fma_vfmadd_ps_256, X86Fmadd,
|
||||
v4f32, v8f32>;
|
||||
memopv8f32, X86Fmadd, v4f32, v8f32>;
|
||||
defm VFMSUBPS : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "ps", memopv4f32,
|
||||
memopv8f32, int_x86_fma_vfmsub_ps,
|
||||
int_x86_fma_vfmsub_ps_256, X86Fmsub,
|
||||
v4f32, v8f32>;
|
||||
memopv8f32, X86Fmsub, v4f32, v8f32>;
|
||||
defm VFMADDSUBPS : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "ps",
|
||||
memopv4f32, memopv8f32,
|
||||
int_x86_fma_vfmaddsub_ps,
|
||||
int_x86_fma_vfmaddsub_ps_256, X86Fmaddsub,
|
||||
memopv4f32, memopv8f32, X86Fmaddsub,
|
||||
v4f32, v8f32>;
|
||||
defm VFMSUBADDPS : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "ps",
|
||||
memopv4f32, memopv8f32,
|
||||
int_x86_fma_vfmsubadd_ps,
|
||||
int_x86_fma_vfmsubadd_ps_256, X86Fmsubadd,
|
||||
memopv4f32, memopv8f32, X86Fmsubadd,
|
||||
v4f32, v8f32>;
|
||||
}
|
||||
|
||||
let ExeDomain = SSEPackedDouble in {
|
||||
defm VFMADDPD : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "pd", memopv2f64,
|
||||
memopv4f64, int_x86_fma_vfmadd_pd,
|
||||
int_x86_fma_vfmadd_pd_256, X86Fmadd, v2f64,
|
||||
v4f64>, VEX_W;
|
||||
memopv4f64, X86Fmadd, v2f64, v4f64>, VEX_W;
|
||||
defm VFMSUBPD : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "pd", memopv2f64,
|
||||
memopv4f64, int_x86_fma_vfmsub_pd,
|
||||
int_x86_fma_vfmsub_pd_256, X86Fmsub, v2f64,
|
||||
v4f64>, VEX_W;
|
||||
memopv4f64, X86Fmsub, v2f64, v4f64>, VEX_W;
|
||||
defm VFMADDSUBPD : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "pd",
|
||||
memopv2f64, memopv4f64,
|
||||
int_x86_fma_vfmaddsub_pd,
|
||||
int_x86_fma_vfmaddsub_pd_256, X86Fmaddsub,
|
||||
memopv2f64, memopv4f64, X86Fmaddsub,
|
||||
v2f64, v4f64>, VEX_W;
|
||||
defm VFMSUBADDPD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "pd",
|
||||
memopv2f64, memopv4f64,
|
||||
int_x86_fma_vfmsubadd_pd,
|
||||
int_x86_fma_vfmsubadd_pd_256, X86Fmsubadd,
|
||||
memopv2f64, memopv4f64, X86Fmsubadd,
|
||||
v2f64, v4f64>, VEX_W;
|
||||
}
|
||||
|
||||
// Fused Negative Multiply-Add
|
||||
let ExeDomain = SSEPackedSingle in {
|
||||
defm VFNMADDPS : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "ps", memopv4f32,
|
||||
memopv8f32, int_x86_fma_vfnmadd_ps,
|
||||
int_x86_fma_vfnmadd_ps_256, X86Fnmadd, v4f32,
|
||||
v8f32>;
|
||||
memopv8f32, X86Fnmadd, v4f32, v8f32>;
|
||||
defm VFNMSUBPS : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "ps", memopv4f32,
|
||||
memopv8f32, int_x86_fma_vfnmsub_ps,
|
||||
int_x86_fma_vfnmsub_ps_256, X86Fnmsub, v4f32,
|
||||
v8f32>;
|
||||
memopv8f32, X86Fnmsub, v4f32, v8f32>;
|
||||
}
|
||||
let ExeDomain = SSEPackedDouble in {
|
||||
defm VFNMADDPD : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "pd", memopv2f64,
|
||||
memopv4f64, int_x86_fma_vfnmadd_pd,
|
||||
int_x86_fma_vfnmadd_pd_256, X86Fnmadd, v2f64,
|
||||
v4f64>, VEX_W;
|
||||
memopv4f64, X86Fnmadd, v2f64, v4f64>, VEX_W;
|
||||
defm VFNMSUBPD : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "pd",
|
||||
memopv2f64,
|
||||
memopv4f64, int_x86_fma_vfnmsub_pd,
|
||||
int_x86_fma_vfnmsub_pd_256, X86Fnmsub, v2f64,
|
||||
memopv2f64, memopv4f64, X86Fnmsub, v2f64,
|
||||
v4f64>, VEX_W;
|
||||
}
|
||||
|
||||
let Predicates = [HasFMA] in {
|
||||
def : Pat<(int_x86_fma_vfmadd_ps VR128:$src2, VR128:$src1, VR128:$src3),
|
||||
(VFMADDPSr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfmadd_ps VR128:$src2, VR128:$src1,
|
||||
(memopv4f32 addr:$src3)),
|
||||
(VFMADDPSr213m VR128:$src1, VR128:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfmsub_ps VR128:$src2, VR128:$src1, VR128:$src3),
|
||||
(VFMSUBPSr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfmsub_ps VR128:$src2, VR128:$src1,
|
||||
(memopv4f32 addr:$src3)),
|
||||
(VFMSUBPSr213m VR128:$src1, VR128:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfmaddsub_ps VR128:$src2, VR128:$src1, VR128:$src3),
|
||||
(VFMADDSUBPSr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfmaddsub_ps VR128:$src2, VR128:$src1,
|
||||
(memopv4f32 addr:$src3)),
|
||||
(VFMADDSUBPSr213m VR128:$src1, VR128:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfmsubadd_ps VR128:$src2, VR128:$src1, VR128:$src3),
|
||||
(VFMSUBADDPSr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfmsubadd_ps VR128:$src2, VR128:$src1,
|
||||
(memopv4f32 addr:$src3)),
|
||||
(VFMSUBADDPSr213m VR128:$src1, VR128:$src2, addr:$src3)>;
|
||||
|
||||
def : Pat<(int_x86_fma_vfmadd_ps_256 VR256:$src2, VR256:$src1, VR256:$src3),
|
||||
(VFMADDPSr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfmadd_ps_256 VR256:$src2, VR256:$src1,
|
||||
(memopv8f32 addr:$src3)),
|
||||
(VFMADDPSr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfmsub_ps_256 VR256:$src2, VR256:$src1, VR256:$src3),
|
||||
(VFMSUBPSr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfmsub_ps_256 VR256:$src2, VR256:$src1,
|
||||
(memopv8f32 addr:$src3)),
|
||||
(VFMSUBPSr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfmaddsub_ps_256 VR256:$src2, VR256:$src1, VR256:$src3),
|
||||
(VFMADDSUBPSr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfmaddsub_ps_256 VR256:$src2, VR256:$src1,
|
||||
(memopv8f32 addr:$src3)),
|
||||
(VFMADDSUBPSr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfmsubadd_ps_256 VR256:$src2, VR256:$src1, VR256:$src3),
|
||||
(VFMSUBADDPSr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfmsubadd_ps_256 VR256:$src2, VR256:$src1,
|
||||
(memopv8f32 addr:$src3)),
|
||||
(VFMSUBADDPSr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
|
||||
|
||||
def : Pat<(int_x86_fma_vfmadd_pd VR128:$src2, VR128:$src1, VR128:$src3),
|
||||
(VFMADDPDr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfmadd_pd VR128:$src2, VR128:$src1,
|
||||
(memopv2f64 addr:$src3)),
|
||||
(VFMADDPDr213m VR128:$src1, VR128:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfmsub_pd VR128:$src2, VR128:$src1, VR128:$src3),
|
||||
(VFMSUBPDr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfmsub_pd VR128:$src2, VR128:$src1,
|
||||
(memopv2f64 addr:$src3)),
|
||||
(VFMSUBPDr213m VR128:$src1, VR128:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfmaddsub_pd VR128:$src2, VR128:$src1, VR128:$src3),
|
||||
(VFMADDSUBPDr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfmaddsub_pd VR128:$src2, VR128:$src1,
|
||||
(memopv2f64 addr:$src3)),
|
||||
(VFMADDSUBPDr213m VR128:$src1, VR128:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfmsubadd_pd VR128:$src2, VR128:$src1, VR128:$src3),
|
||||
(VFMSUBADDPDr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfmsubadd_pd VR128:$src2, VR128:$src1,
|
||||
(memopv2f64 addr:$src3)),
|
||||
(VFMSUBADDPDr213m VR128:$src1, VR128:$src2, addr:$src3)>;
|
||||
|
||||
def : Pat<(int_x86_fma_vfmadd_pd_256 VR256:$src2, VR256:$src1, VR256:$src3),
|
||||
(VFMADDPDr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfmadd_pd_256 VR256:$src2, VR256:$src1,
|
||||
(memopv4f64 addr:$src3)),
|
||||
(VFMADDPDr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfmsub_pd_256 VR256:$src2, VR256:$src1, VR256:$src3),
|
||||
(VFMSUBPDr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfmsub_pd_256 VR256:$src2, VR256:$src1,
|
||||
(memopv4f64 addr:$src3)),
|
||||
(VFMSUBPDr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfmaddsub_pd_256 VR256:$src2, VR256:$src1, VR256:$src3),
|
||||
(VFMADDSUBPDr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfmaddsub_pd_256 VR256:$src2, VR256:$src1,
|
||||
(memopv4f64 addr:$src3)),
|
||||
(VFMADDSUBPDr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfmsubadd_pd_256 VR256:$src2, VR256:$src1, VR256:$src3),
|
||||
(VFMSUBADDPDr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfmsubadd_pd_256 VR256:$src2, VR256:$src1,
|
||||
(memopv4f64 addr:$src3)),
|
||||
(VFMSUBADDPDr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
|
||||
|
||||
def : Pat<(int_x86_fma_vfnmadd_ps VR128:$src2, VR128:$src1, VR128:$src3),
|
||||
(VFNMADDPSr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfnmadd_ps VR128:$src2, VR128:$src1,
|
||||
(memopv4f32 addr:$src3)),
|
||||
(VFNMADDPSr213m VR128:$src1, VR128:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfnmsub_ps VR128:$src2, VR128:$src1, VR128:$src3),
|
||||
(VFNMSUBPSr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfnmsub_ps VR128:$src2, VR128:$src1,
|
||||
(memopv4f32 addr:$src3)),
|
||||
(VFNMSUBPSr213m VR128:$src1, VR128:$src2, addr:$src3)>;
|
||||
|
||||
def : Pat<(int_x86_fma_vfnmadd_ps_256 VR256:$src2, VR256:$src1, VR256:$src3),
|
||||
(VFNMADDPSr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfnmadd_ps_256 VR256:$src2, VR256:$src1,
|
||||
(memopv8f32 addr:$src3)),
|
||||
(VFNMADDPSr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfnmsub_ps_256 VR256:$src2, VR256:$src1, VR256:$src3),
|
||||
(VFNMSUBPSr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfnmsub_ps_256 VR256:$src2, VR256:$src1,
|
||||
(memopv8f32 addr:$src3)),
|
||||
(VFNMSUBPSr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
|
||||
|
||||
def : Pat<(int_x86_fma_vfnmadd_pd VR128:$src2, VR128:$src1, VR128:$src3),
|
||||
(VFNMADDPDr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfnmadd_pd VR128:$src2, VR128:$src1,
|
||||
(memopv2f64 addr:$src3)),
|
||||
(VFNMADDPDr213m VR128:$src1, VR128:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfnmsub_pd VR128:$src2, VR128:$src1, VR128:$src3),
|
||||
(VFNMSUBPDr213r VR128:$src1, VR128:$src2, VR128:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfnmsub_pd VR128:$src2, VR128:$src1,
|
||||
(memopv2f64 addr:$src3)),
|
||||
(VFNMSUBPDr213m VR128:$src1, VR128:$src2, addr:$src3)>;
|
||||
|
||||
def : Pat<(int_x86_fma_vfnmadd_pd_256 VR256:$src2, VR256:$src1, VR256:$src3),
|
||||
(VFNMADDPDr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfnmadd_pd_256 VR256:$src2, VR256:$src1,
|
||||
(memopv4f64 addr:$src3)),
|
||||
(VFNMADDPDr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfnmsub_pd_256 VR256:$src2, VR256:$src1, VR256:$src3),
|
||||
(VFNMSUBPDr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
|
||||
def : Pat<(int_x86_fma_vfnmsub_pd_256 VR256:$src2, VR256:$src1,
|
||||
(memopv4f64 addr:$src3)),
|
||||
(VFNMSUBPDr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
|
||||
|
||||
} // Predicates = [HasFMA]
|
||||
|
||||
let Constraints = "$src1 = $dst" in {
|
||||
multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop,
|
||||
RegisterClass RC> {
|
||||
|
|
|
|||
|
|
@ -1145,10 +1145,6 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
|
|||
{ X86::VFMADDPDr132rY, X86::VFMADDPDr132mY, TB_ALIGN_32 },
|
||||
{ X86::VFMADDPSr213rY, X86::VFMADDPSr213mY, TB_ALIGN_32 },
|
||||
{ X86::VFMADDPDr213rY, X86::VFMADDPDr213mY, TB_ALIGN_32 },
|
||||
{ X86::VFMADDPSr213r_Int, X86::VFMADDPSr213m_Int, TB_ALIGN_16 },
|
||||
{ X86::VFMADDPDr213r_Int, X86::VFMADDPDr213m_Int, TB_ALIGN_16 },
|
||||
{ X86::VFMADDPSr213rY_Int, X86::VFMADDPSr213mY_Int, TB_ALIGN_32 },
|
||||
{ X86::VFMADDPDr213rY_Int, X86::VFMADDPDr213mY_Int, TB_ALIGN_32 },
|
||||
|
||||
{ X86::VFNMADDSSr231r, X86::VFNMADDSSr231m, 0 },
|
||||
{ X86::VFNMADDSDr231r, X86::VFNMADDSDr231m, 0 },
|
||||
|
|
@ -1171,10 +1167,6 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
|
|||
{ X86::VFNMADDPDr132rY, X86::VFNMADDPDr132mY, TB_ALIGN_32 },
|
||||
{ X86::VFNMADDPSr213rY, X86::VFNMADDPSr213mY, TB_ALIGN_32 },
|
||||
{ X86::VFNMADDPDr213rY, X86::VFNMADDPDr213mY, TB_ALIGN_32 },
|
||||
{ X86::VFNMADDPSr213r_Int, X86::VFNMADDPSr213m_Int, TB_ALIGN_16 },
|
||||
{ X86::VFNMADDPDr213r_Int, X86::VFNMADDPDr213m_Int, TB_ALIGN_16 },
|
||||
{ X86::VFNMADDPSr213rY_Int, X86::VFNMADDPSr213mY_Int, TB_ALIGN_32 },
|
||||
{ X86::VFNMADDPDr213rY_Int, X86::VFNMADDPDr213mY_Int, TB_ALIGN_32 },
|
||||
|
||||
{ X86::VFMSUBSSr231r, X86::VFMSUBSSr231m, 0 },
|
||||
{ X86::VFMSUBSDr231r, X86::VFMSUBSDr231m, 0 },
|
||||
|
|
@ -1197,10 +1189,6 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
|
|||
{ X86::VFMSUBPDr132rY, X86::VFMSUBPDr132mY, TB_ALIGN_32 },
|
||||
{ X86::VFMSUBPSr213rY, X86::VFMSUBPSr213mY, TB_ALIGN_32 },
|
||||
{ X86::VFMSUBPDr213rY, X86::VFMSUBPDr213mY, TB_ALIGN_32 },
|
||||
{ X86::VFMSUBPSr213r_Int, X86::VFMSUBPSr213m_Int, TB_ALIGN_16 },
|
||||
{ X86::VFMSUBPDr213r_Int, X86::VFMSUBPDr213m_Int, TB_ALIGN_16 },
|
||||
{ X86::VFMSUBPSr213rY_Int, X86::VFMSUBPSr213mY_Int, TB_ALIGN_32 },
|
||||
{ X86::VFMSUBPDr213rY_Int, X86::VFMSUBPDr213mY_Int, TB_ALIGN_32 },
|
||||
|
||||
{ X86::VFNMSUBSSr231r, X86::VFNMSUBSSr231m, 0 },
|
||||
{ X86::VFNMSUBSDr231r, X86::VFNMSUBSDr231m, 0 },
|
||||
|
|
@ -1223,10 +1211,6 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
|
|||
{ X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr132mY, TB_ALIGN_32 },
|
||||
{ X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr213mY, TB_ALIGN_32 },
|
||||
{ X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr213mY, TB_ALIGN_32 },
|
||||
{ X86::VFNMSUBPSr213r_Int, X86::VFNMSUBPSr213m_Int, TB_ALIGN_16 },
|
||||
{ X86::VFNMSUBPDr213r_Int, X86::VFNMSUBPDr213m_Int, TB_ALIGN_16 },
|
||||
{ X86::VFNMSUBPSr213rY_Int, X86::VFNMSUBPSr213mY_Int, TB_ALIGN_32 },
|
||||
{ X86::VFNMSUBPDr213rY_Int, X86::VFNMSUBPDr213mY_Int, TB_ALIGN_32 },
|
||||
|
||||
{ X86::VFMADDSUBPSr231r, X86::VFMADDSUBPSr231m, TB_ALIGN_16 },
|
||||
{ X86::VFMADDSUBPDr231r, X86::VFMADDSUBPDr231m, TB_ALIGN_16 },
|
||||
|
|
@ -1240,10 +1224,6 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
|
|||
{ X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr132mY, TB_ALIGN_32 },
|
||||
{ X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr213mY, TB_ALIGN_32 },
|
||||
{ X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr213mY, TB_ALIGN_32 },
|
||||
{ X86::VFMADDSUBPSr213r_Int, X86::VFMADDSUBPSr213m_Int, TB_ALIGN_16 },
|
||||
{ X86::VFMADDSUBPDr213r_Int, X86::VFMADDSUBPDr213m_Int, TB_ALIGN_16 },
|
||||
{ X86::VFMADDSUBPSr213rY_Int, X86::VFMADDSUBPSr213mY_Int, TB_ALIGN_32 },
|
||||
{ X86::VFMADDSUBPDr213rY_Int, X86::VFMADDSUBPDr213mY_Int, TB_ALIGN_32 },
|
||||
|
||||
{ X86::VFMSUBADDPSr231r, X86::VFMSUBADDPSr231m, TB_ALIGN_16 },
|
||||
{ X86::VFMSUBADDPDr231r, X86::VFMSUBADDPDr231m, TB_ALIGN_16 },
|
||||
|
|
@ -1257,10 +1237,6 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
|
|||
{ X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr132mY, TB_ALIGN_32 },
|
||||
{ X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr213mY, TB_ALIGN_32 },
|
||||
{ X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr213mY, TB_ALIGN_32 },
|
||||
{ X86::VFMSUBADDPSr213r_Int, X86::VFMSUBADDPSr213m_Int, TB_ALIGN_16 },
|
||||
{ X86::VFMSUBADDPDr213r_Int, X86::VFMSUBADDPDr213m_Int, TB_ALIGN_16 },
|
||||
{ X86::VFMSUBADDPSr213rY_Int, X86::VFMSUBADDPSr213mY_Int, TB_ALIGN_32 },
|
||||
{ X86::VFMSUBADDPDr213rY_Int, X86::VFMSUBADDPDr213mY_Int, TB_ALIGN_32 },
|
||||
};
|
||||
|
||||
for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue