forked from OSchip/llvm-project
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9d68302e48
commit
b566ab7b97
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@ -132,6 +132,24 @@ def tPICADD : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, pclabel:$cp),
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"$cp:\n\tadd $dst, pc",
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"$cp:\n\tadd $dst, pc",
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[(set tGPR:$dst, (ARMpic_add tGPR:$lhs, imm:$cp))]>;
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[(set tGPR:$dst, (ARMpic_add tGPR:$lhs, imm:$cp))]>;
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// PC relative add.
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def tADDrPCi : T1I<(outs tGPR:$dst), (ins i32imm:$rhs),
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"add $dst, pc, $rhs * 4", []>;
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// ADD rd, sp, #imm8
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// FIXME: hard code sp?
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def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, i32imm:$rhs),
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"add $dst, $sp, $rhs * 4 @ addrspi", []>;
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// ADD sp, sp, #imm7
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// FIXME: hard code sp?
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def tADDspi : T1It<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
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"add $dst, $rhs * 4", []>;
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// FIXME: Make use of the following?
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// ADD rm, sp, rm
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// ADD sp, rm
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Control Flow Instructions.
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// Control Flow Instructions.
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//
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//
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@ -303,15 +321,6 @@ let neverHasSideEffects = 1 in
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def tADDhirr : T1It<(outs tGPR:$dst), (ins GPR:$lhs, GPR:$rhs),
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def tADDhirr : T1It<(outs tGPR:$dst), (ins GPR:$lhs, GPR:$rhs),
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"add $dst, $rhs @ addhirr", []>;
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"add $dst, $rhs @ addhirr", []>;
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def tADDrPCi : T1I<(outs tGPR:$dst), (ins i32imm:$rhs),
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"add $dst, pc, $rhs * 4", []>;
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def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, i32imm:$rhs),
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"add $dst, $sp, $rhs * 4 @ addrspi", []>;
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def tADDspi : T1It<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
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"add $dst, $rhs * 4", []>;
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let isCommutable = 1 in
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let isCommutable = 1 in
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def tAND : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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def tAND : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"and $dst, $rhs",
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"and $dst, $rhs",
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