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[ARM] Replace ARMISD::RBIT with ISD::BITREVERSE 

ISD::BITREVERSE matches "rbit" completely, so remove ARMISD::RBIT and mark ISD::BITREVERSE as legal, adding a test for lowering.

llvm-svn: 253047
This commit is contained in:
James Molloy 2015-11-13 16:05:22 +00:00
parent 3e43cda61c
commit b564098c62
6 changed files with 19 additions and 10 deletions
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1
llvm/include/llvm/Target/TargetSelectionDAG.td
View File

@ -393,6 +393,7 @@ def umax : SDNode<"ISD::UMAX" , SDTIntBinOp>;
def sabsdiff : SDNode<"ISD::SABSDIFF" , SDTIntBinOp>;
def uabsdiff : SDNode<"ISD::UABSDIFF" , SDTIntBinOp>;
def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
def bitreverse : SDNode<"ISD::BITREVERSE" , SDTIntUnaryOp>;
def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;

9
llvm/lib/Target/ARM/ARMISelLowering.cpp
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@ -745,6 +745,9 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::SUBE, MVT::i32, Custom);
}
if (!Subtarget->isThumb1Only())
setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
// ARM does not have ROTL.
setOperationAction(ISD::ROTL, MVT::i32, Expand);
for (MVT VT : MVT::vector_valuetypes()) {
@ -1129,8 +1132,6 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
case ARMISD::CMOV: return "ARMISD::CMOV";
case ARMISD::RBIT: return "ARMISD::RBIT";
case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
case ARMISD::RRX: return "ARMISD::RRX";
@ -2797,7 +2798,7 @@ ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
case Intrinsic::arm_rbit: {
assert(Op.getOperand(1).getValueType() == MVT::i32 &&
"RBIT intrinsic must have i32 type!");
return DAG.getNode(ARMISD::RBIT, dl, MVT::i32, Op.getOperand(1));
return DAG.getNode(ISD::BITREVERSE, dl, MVT::i32, Op.getOperand(1));
}
case Intrinsic::arm_thread_pointer: {
EVT PtrVT = getPointerTy(DAG.getDataLayout());
@ -4376,7 +4377,7 @@ static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
if (!ST->hasV6T2Ops())
return SDValue();
SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
SDValue rbit = DAG.getNode(ISD::BITREVERSE, dl, VT, N->getOperand(0));
return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
}

2
llvm/lib/Target/ARM/ARMISelLowering.h
View File

@ -63,8 +63,6 @@ namespace llvm {
BCC_i64,
RBIT, // ARM bitreverse instruction
SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.

4
llvm/lib/Target/ARM/ARMInstrInfo.td
View File

@ -176,8 +176,6 @@ def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
[SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
@ -4194,7 +4192,7 @@ def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
IIC_iUNAr, "rbit", "\t$Rd, $Rm",
[(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
[(set GPR:$Rd, (bitreverse GPR:$Rm))]>,
Requires<[IsARM, HasV6T2]>,
Sched<[WriteALU]>;

2
llvm/lib/Target/ARM/ARMInstrThumb2.td
View File

@ -2964,7 +2964,7 @@ def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
"rbit", "\t$Rd, $Rm",
[(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>,
[(set rGPR:$Rd, (bitreverse rGPR:$Rm))]>,
Sched<[WriteALU]>;
def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,

11
llvm/test/CodeGen/ARM/rbit.ll
View File

@ -18,3 +18,14 @@ entry:
}
declare i32 @llvm.arm.rbit(i32)
declare i32 @llvm.bitreverse.i32(i32) readnone
; CHECK-LABEL: rbit_generic
; CHECK: rbit r0, r0
define i32 @rbit_generic(i32 %t) {
entry:
%rbit = call i32 @llvm.bitreverse.i32(i32 %t)
ret i32 %rbit
}