forked from OSchip/llvm-project
[AArch64] More @llvm.fma.f16 tests
Follow up of rL371321 that added FMA FP16 patterns. This adds more tests for @llvm.fma.f16. This probably shows we miss one fmsub optimisation opportunity, which I will look into. llvm-svn: 371833
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@ -1,6 +1,4 @@
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; RUN: llc < %s -mtriple=aarch64-eabi -mattr=+v8.2a,+fullfp16 | FileCheck %s
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declare half @llvm.fma.f16(half, half, half)
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; RUN: llc < %s -mtriple=aarch64-eabi -mattr=+v8.2a,+neon,+fullfp16 | FileCheck %s
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define dso_local half @t_vfmah_f16(half %a, half %b, half %c) {
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; CHECK-LABEL: t_vfmah_f16:
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@ -11,3 +9,45 @@ entry:
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ret half %0
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}
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define half @fnma16(half %a, half %b, half %c) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: fnma16:
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; CHECK: fnmadd h0, h0, h1, h2
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%0 = tail call half @llvm.fma.f16(half %a, half %b, half %c)
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%mul = fmul half %0, -1.000000e+00
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ret half %mul
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}
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define half @fms16(half %a, half %b, half %c) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: fms16:
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; CHECK: fmsub h0, h0, h1, h2
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%mul = fmul half %b, -1.000000e+00
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%0 = tail call half @llvm.fma.f16(half %a, half %mul, half %c)
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ret half %0
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}
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define half @fms16_com(half %a, half %b, half %c) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: fms16_com:
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; FIXME: This should be a fmsub.
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; CHECK: fneg h1, h1
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; CHECK-NEXT: fmadd h0, h1, h0, h2
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%mul = fmul half %b, -1.000000e+00
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%0 = tail call half @llvm.fma.f16(half %mul, half %a, half %c)
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ret half %0
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}
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define half @fnms16(half %a, half %b, half %c) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: fnms16:
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; CHECK: fnmsub h0, h0, h1, h2
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%mul = fmul half %c, -1.000000e+00
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%0 = tail call half @llvm.fma.f16(half %a, half %b, half %mul)
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ret half %0
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}
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declare half @llvm.fma.f16(half, half, half)
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