From b5498cbf64e56af50d3c9ca9b415ffbb5faa00d9 Mon Sep 17 00:00:00 2001 From: Alex Bradbury Date: Sat, 30 Mar 2019 15:53:38 +0000 Subject: [PATCH] [RISCV] Add RV64 CHECK lines to test/CodeGen/RISCV/vararg.ll and prepare for hard float tests vararg.ll previously missed RV64 tests. This patch also prepares for using vararg.ll to test handling of varargs for the ilp32f/ilp32d/lp64f/lp64d hard float ABIs. In these ABIs, varargs are passed as in either the ilp32 or lp64 ABI. Due to some slight codegen differences, different check lines are needed for when RV32D is enabled. llvm-svn: 357350 --- llvm/test/CodeGen/RISCV/vararg.ll | 2173 ++++++++++++++++++++--------- 1 file changed, 1542 insertions(+), 631 deletions(-) diff --git a/llvm/test/CodeGen/RISCV/vararg.ll b/llvm/test/CodeGen/RISCV/vararg.ll index 7c1e48836bed..5486314af1dc 100644 --- a/llvm/test/CodeGen/RISCV/vararg.ll +++ b/llvm/test/CodeGen/RISCV/vararg.ll @@ -1,8 +1,20 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ -; RUN: | FileCheck -check-prefix=RV32I-FPELIM %s +; RUN: | FileCheck -check-prefix=ILP32-ILP32F-FPELIM %s ; RUN: llc -mtriple=riscv32 -verify-machineinstrs -frame-pointer=all < %s \ -; RUN: | FileCheck -check-prefix=RV32I-WITHFP %s +; RUN: | FileCheck -check-prefix=ILP32-ILP32F-WITHFP %s +; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=RV32D-ILP32-ILP32F-ILP32D-FPELIM %s +; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=LP64-LP64F-LP64D-FPELIM %s +; RUN: llc -mtriple=riscv64 -verify-machineinstrs -frame-pointer=all < %s \ +; RUN: | FileCheck -check-prefix=LP64-LP64F-LP64D-WITHFP %s + +; TODO: RUN lines for ilp32f/ilp32d/lp64f/lp64d must be added when hard float +; ABI Support lands. The same vararg calling convention is used for +; ilp32/ilp32f/ilp32d and for lp64/lp64f/lp64d. Different CHECK lines are +; required for RV32D due to slight codegen differences due to the way the +; f64 load operations are lowered. declare void @llvm.va_start(i8*) declare void @llvm.va_end(i8*) @@ -14,42 +26,97 @@ declare void @notdead(i8*) ; lowered correctly define i32 @va1(i8* %fmt, ...) nounwind { -; RV32I-FPELIM-LABEL: va1: -; RV32I-FPELIM: # %bb.0: -; RV32I-FPELIM-NEXT: addi sp, sp, -48 -; RV32I-FPELIM-NEXT: mv a0, a1 -; RV32I-FPELIM-NEXT: sw a7, 44(sp) -; RV32I-FPELIM-NEXT: sw a6, 40(sp) -; RV32I-FPELIM-NEXT: sw a5, 36(sp) -; RV32I-FPELIM-NEXT: sw a4, 32(sp) -; RV32I-FPELIM-NEXT: sw a3, 28(sp) -; RV32I-FPELIM-NEXT: sw a2, 24(sp) -; RV32I-FPELIM-NEXT: addi a1, sp, 24 -; RV32I-FPELIM-NEXT: sw a1, 12(sp) -; RV32I-FPELIM-NEXT: sw a0, 20(sp) -; RV32I-FPELIM-NEXT: addi sp, sp, 48 -; RV32I-FPELIM-NEXT: ret +; ILP32-ILP32F-FPELIM-LABEL: va1: +; ILP32-ILP32F-FPELIM: # %bb.0: +; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -48 +; ILP32-ILP32F-FPELIM-NEXT: mv a0, a1 +; ILP32-ILP32F-FPELIM-NEXT: sw a7, 44(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a6, 40(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a5, 36(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a4, 32(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a3, 28(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a2, 24(sp) +; ILP32-ILP32F-FPELIM-NEXT: addi a1, sp, 24 +; ILP32-ILP32F-FPELIM-NEXT: sw a1, 12(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a0, 20(sp) +; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48 +; ILP32-ILP32F-FPELIM-NEXT: ret ; -; RV32I-WITHFP-LABEL: va1: -; RV32I-WITHFP: # %bb.0: -; RV32I-WITHFP-NEXT: addi sp, sp, -48 -; RV32I-WITHFP-NEXT: sw ra, 12(sp) -; RV32I-WITHFP-NEXT: sw s0, 8(sp) -; RV32I-WITHFP-NEXT: addi s0, sp, 16 -; RV32I-WITHFP-NEXT: mv a0, a1 -; RV32I-WITHFP-NEXT: sw a7, 28(s0) -; RV32I-WITHFP-NEXT: sw a6, 24(s0) -; RV32I-WITHFP-NEXT: sw a5, 20(s0) -; RV32I-WITHFP-NEXT: sw a4, 16(s0) -; RV32I-WITHFP-NEXT: sw a3, 12(s0) -; RV32I-WITHFP-NEXT: sw a2, 8(s0) -; RV32I-WITHFP-NEXT: addi a1, s0, 8 -; RV32I-WITHFP-NEXT: sw a1, -12(s0) -; RV32I-WITHFP-NEXT: sw a0, 4(s0) -; RV32I-WITHFP-NEXT: lw s0, 8(sp) -; RV32I-WITHFP-NEXT: lw ra, 12(sp) -; RV32I-WITHFP-NEXT: addi sp, sp, 48 -; RV32I-WITHFP-NEXT: ret +; ILP32-ILP32F-WITHFP-LABEL: va1: +; ILP32-ILP32F-WITHFP: # %bb.0: +; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48 +; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp) +; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) +; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16 +; ILP32-ILP32F-WITHFP-NEXT: mv a0, a1 +; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0) +; ILP32-ILP32F-WITHFP-NEXT: addi a1, s0, 8 +; ILP32-ILP32F-WITHFP-NEXT: sw a1, -12(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a0, 4(s0) +; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) +; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) +; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48 +; ILP32-ILP32F-WITHFP-NEXT: ret +; +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va1: +; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a0, a1 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 44(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 36(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 32(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 28(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 24(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, sp, 24 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 12(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 20(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 48 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret +; +; LP64-LP64F-LP64D-FPELIM-LABEL: va1: +; LP64-LP64F-LP64D-FPELIM: # %bb.0: +; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -80 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 24(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a7, 72(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a6, 64(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 56(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 48(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 40(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 32(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, sp, 24 +; LP64-LP64F-LP64D-FPELIM-NEXT: ori a0, a0, 4 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: lw a0, 24(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 80 +; LP64-LP64F-LP64D-FPELIM-NEXT: ret +; +; LP64-LP64F-LP64D-WITHFP-LABEL: va1: +; LP64-LP64F-LP64D-WITHFP: # %bb.0: +; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -96 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 8 +; LP64-LP64F-LP64D-WITHFP-NEXT: ori a0, a0, 4 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -24(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: lw a0, 8(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 96 +; LP64-LP64F-LP64D-WITHFP-NEXT: ret %va = alloca i8*, align 4 %1 = bitcast i8** %va to i8* call void @llvm.va_start(i8* %1) @@ -63,42 +130,97 @@ define i32 @va1(i8* %fmt, ...) nounwind { } define i32 @va1_va_arg(i8* %fmt, ...) nounwind { -; RV32I-FPELIM-LABEL: va1_va_arg: -; RV32I-FPELIM: # %bb.0: -; RV32I-FPELIM-NEXT: addi sp, sp, -48 -; RV32I-FPELIM-NEXT: mv a0, a1 -; RV32I-FPELIM-NEXT: sw a7, 44(sp) -; RV32I-FPELIM-NEXT: sw a6, 40(sp) -; RV32I-FPELIM-NEXT: sw a5, 36(sp) -; RV32I-FPELIM-NEXT: sw a4, 32(sp) -; RV32I-FPELIM-NEXT: sw a3, 28(sp) -; RV32I-FPELIM-NEXT: sw a2, 24(sp) -; RV32I-FPELIM-NEXT: addi a1, sp, 24 -; RV32I-FPELIM-NEXT: sw a1, 12(sp) -; RV32I-FPELIM-NEXT: sw a0, 20(sp) -; RV32I-FPELIM-NEXT: addi sp, sp, 48 -; RV32I-FPELIM-NEXT: ret +; ILP32-ILP32F-FPELIM-LABEL: va1_va_arg: +; ILP32-ILP32F-FPELIM: # %bb.0: +; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -48 +; ILP32-ILP32F-FPELIM-NEXT: mv a0, a1 +; ILP32-ILP32F-FPELIM-NEXT: sw a7, 44(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a6, 40(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a5, 36(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a4, 32(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a3, 28(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a2, 24(sp) +; ILP32-ILP32F-FPELIM-NEXT: addi a1, sp, 24 +; ILP32-ILP32F-FPELIM-NEXT: sw a1, 12(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a0, 20(sp) +; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48 +; ILP32-ILP32F-FPELIM-NEXT: ret ; -; RV32I-WITHFP-LABEL: va1_va_arg: -; RV32I-WITHFP: # %bb.0: -; RV32I-WITHFP-NEXT: addi sp, sp, -48 -; RV32I-WITHFP-NEXT: sw ra, 12(sp) -; RV32I-WITHFP-NEXT: sw s0, 8(sp) -; RV32I-WITHFP-NEXT: addi s0, sp, 16 -; RV32I-WITHFP-NEXT: mv a0, a1 -; RV32I-WITHFP-NEXT: sw a7, 28(s0) -; RV32I-WITHFP-NEXT: sw a6, 24(s0) -; RV32I-WITHFP-NEXT: sw a5, 20(s0) -; RV32I-WITHFP-NEXT: sw a4, 16(s0) -; RV32I-WITHFP-NEXT: sw a3, 12(s0) -; RV32I-WITHFP-NEXT: sw a2, 8(s0) -; RV32I-WITHFP-NEXT: addi a1, s0, 8 -; RV32I-WITHFP-NEXT: sw a1, -12(s0) -; RV32I-WITHFP-NEXT: sw a0, 4(s0) -; RV32I-WITHFP-NEXT: lw s0, 8(sp) -; RV32I-WITHFP-NEXT: lw ra, 12(sp) -; RV32I-WITHFP-NEXT: addi sp, sp, 48 -; RV32I-WITHFP-NEXT: ret +; ILP32-ILP32F-WITHFP-LABEL: va1_va_arg: +; ILP32-ILP32F-WITHFP: # %bb.0: +; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48 +; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp) +; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) +; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16 +; ILP32-ILP32F-WITHFP-NEXT: mv a0, a1 +; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0) +; ILP32-ILP32F-WITHFP-NEXT: addi a1, s0, 8 +; ILP32-ILP32F-WITHFP-NEXT: sw a1, -12(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a0, 4(s0) +; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) +; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) +; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48 +; ILP32-ILP32F-WITHFP-NEXT: ret +; +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va1_va_arg: +; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a0, a1 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 44(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 36(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 32(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 28(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 24(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, sp, 24 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 12(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 20(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 48 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret +; +; LP64-LP64F-LP64D-FPELIM-LABEL: va1_va_arg: +; LP64-LP64F-LP64D-FPELIM: # %bb.0: +; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -80 +; LP64-LP64F-LP64D-FPELIM-NEXT: mv a0, a1 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a7, 72(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a6, 64(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 56(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 48(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 40(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 32(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, sp, 24 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, a1, 8 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 8(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 24(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 80 +; LP64-LP64F-LP64D-FPELIM-NEXT: ret +; +; LP64-LP64F-LP64D-WITHFP-LABEL: va1_va_arg: +; LP64-LP64F-LP64D-WITHFP: # %bb.0: +; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -96 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32 +; LP64-LP64F-LP64D-WITHFP-NEXT: mv a0, a1 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, s0, 8 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, a1, 8 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, -24(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, 8(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 96 +; LP64-LP64F-LP64D-WITHFP-NEXT: ret %va = alloca i8*, align 4 %1 = bitcast i8** %va to i8* call void @llvm.va_start(i8* %1) @@ -110,65 +232,167 @@ define i32 @va1_va_arg(i8* %fmt, ...) nounwind { ; Ensure the adjustment when restoring the stack pointer using the frame ; pointer is correct define i32 @va1_va_arg_alloca(i8* %fmt, ...) nounwind { -; RV32I-FPELIM-LABEL: va1_va_arg_alloca: -; RV32I-FPELIM: # %bb.0: -; RV32I-FPELIM-NEXT: addi sp, sp, -48 -; RV32I-FPELIM-NEXT: sw ra, 12(sp) -; RV32I-FPELIM-NEXT: sw s0, 8(sp) -; RV32I-FPELIM-NEXT: sw s1, 4(sp) -; RV32I-FPELIM-NEXT: addi s0, sp, 16 -; RV32I-FPELIM-NEXT: mv s1, a1 -; RV32I-FPELIM-NEXT: sw a7, 28(s0) -; RV32I-FPELIM-NEXT: sw a6, 24(s0) -; RV32I-FPELIM-NEXT: sw a5, 20(s0) -; RV32I-FPELIM-NEXT: sw a4, 16(s0) -; RV32I-FPELIM-NEXT: sw a3, 12(s0) -; RV32I-FPELIM-NEXT: sw a2, 8(s0) -; RV32I-FPELIM-NEXT: addi a0, s0, 8 -; RV32I-FPELIM-NEXT: sw a0, -16(s0) -; RV32I-FPELIM-NEXT: sw a1, 4(s0) -; RV32I-FPELIM-NEXT: addi a0, a1, 15 -; RV32I-FPELIM-NEXT: andi a0, a0, -16 -; RV32I-FPELIM-NEXT: sub a0, sp, a0 -; RV32I-FPELIM-NEXT: mv sp, a0 -; RV32I-FPELIM-NEXT: call notdead -; RV32I-FPELIM-NEXT: mv a0, s1 -; RV32I-FPELIM-NEXT: addi sp, s0, -16 -; RV32I-FPELIM-NEXT: lw s1, 4(sp) -; RV32I-FPELIM-NEXT: lw s0, 8(sp) -; RV32I-FPELIM-NEXT: lw ra, 12(sp) -; RV32I-FPELIM-NEXT: addi sp, sp, 48 -; RV32I-FPELIM-NEXT: ret +; ILP32-ILP32F-FPELIM-LABEL: va1_va_arg_alloca: +; ILP32-ILP32F-FPELIM: # %bb.0: +; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -48 +; ILP32-ILP32F-FPELIM-NEXT: sw ra, 12(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw s0, 8(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw s1, 4(sp) +; ILP32-ILP32F-FPELIM-NEXT: addi s0, sp, 16 +; ILP32-ILP32F-FPELIM-NEXT: mv s1, a1 +; ILP32-ILP32F-FPELIM-NEXT: sw a7, 28(s0) +; ILP32-ILP32F-FPELIM-NEXT: sw a6, 24(s0) +; ILP32-ILP32F-FPELIM-NEXT: sw a5, 20(s0) +; ILP32-ILP32F-FPELIM-NEXT: sw a4, 16(s0) +; ILP32-ILP32F-FPELIM-NEXT: sw a3, 12(s0) +; ILP32-ILP32F-FPELIM-NEXT: sw a2, 8(s0) +; ILP32-ILP32F-FPELIM-NEXT: addi a0, s0, 8 +; ILP32-ILP32F-FPELIM-NEXT: sw a0, -16(s0) +; ILP32-ILP32F-FPELIM-NEXT: sw a1, 4(s0) +; ILP32-ILP32F-FPELIM-NEXT: addi a0, a1, 15 +; ILP32-ILP32F-FPELIM-NEXT: andi a0, a0, -16 +; ILP32-ILP32F-FPELIM-NEXT: sub a0, sp, a0 +; ILP32-ILP32F-FPELIM-NEXT: mv sp, a0 +; ILP32-ILP32F-FPELIM-NEXT: call notdead +; ILP32-ILP32F-FPELIM-NEXT: mv a0, s1 +; ILP32-ILP32F-FPELIM-NEXT: addi sp, s0, -16 +; ILP32-ILP32F-FPELIM-NEXT: lw s1, 4(sp) +; ILP32-ILP32F-FPELIM-NEXT: lw s0, 8(sp) +; ILP32-ILP32F-FPELIM-NEXT: lw ra, 12(sp) +; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48 +; ILP32-ILP32F-FPELIM-NEXT: ret ; -; RV32I-WITHFP-LABEL: va1_va_arg_alloca: -; RV32I-WITHFP: # %bb.0: -; RV32I-WITHFP-NEXT: addi sp, sp, -48 -; RV32I-WITHFP-NEXT: sw ra, 12(sp) -; RV32I-WITHFP-NEXT: sw s0, 8(sp) -; RV32I-WITHFP-NEXT: sw s1, 4(sp) -; RV32I-WITHFP-NEXT: addi s0, sp, 16 -; RV32I-WITHFP-NEXT: mv s1, a1 -; RV32I-WITHFP-NEXT: sw a7, 28(s0) -; RV32I-WITHFP-NEXT: sw a6, 24(s0) -; RV32I-WITHFP-NEXT: sw a5, 20(s0) -; RV32I-WITHFP-NEXT: sw a4, 16(s0) -; RV32I-WITHFP-NEXT: sw a3, 12(s0) -; RV32I-WITHFP-NEXT: sw a2, 8(s0) -; RV32I-WITHFP-NEXT: addi a0, s0, 8 -; RV32I-WITHFP-NEXT: sw a0, -16(s0) -; RV32I-WITHFP-NEXT: sw a1, 4(s0) -; RV32I-WITHFP-NEXT: addi a0, a1, 15 -; RV32I-WITHFP-NEXT: andi a0, a0, -16 -; RV32I-WITHFP-NEXT: sub a0, sp, a0 -; RV32I-WITHFP-NEXT: mv sp, a0 -; RV32I-WITHFP-NEXT: call notdead -; RV32I-WITHFP-NEXT: mv a0, s1 -; RV32I-WITHFP-NEXT: addi sp, s0, -16 -; RV32I-WITHFP-NEXT: lw s1, 4(sp) -; RV32I-WITHFP-NEXT: lw s0, 8(sp) -; RV32I-WITHFP-NEXT: lw ra, 12(sp) -; RV32I-WITHFP-NEXT: addi sp, sp, 48 -; RV32I-WITHFP-NEXT: ret +; ILP32-ILP32F-WITHFP-LABEL: va1_va_arg_alloca: +; ILP32-ILP32F-WITHFP: # %bb.0: +; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48 +; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp) +; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) +; ILP32-ILP32F-WITHFP-NEXT: sw s1, 4(sp) +; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16 +; ILP32-ILP32F-WITHFP-NEXT: mv s1, a1 +; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0) +; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 8 +; ILP32-ILP32F-WITHFP-NEXT: sw a0, -16(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0) +; ILP32-ILP32F-WITHFP-NEXT: addi a0, a1, 15 +; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -16 +; ILP32-ILP32F-WITHFP-NEXT: sub a0, sp, a0 +; ILP32-ILP32F-WITHFP-NEXT: mv sp, a0 +; ILP32-ILP32F-WITHFP-NEXT: call notdead +; ILP32-ILP32F-WITHFP-NEXT: mv a0, s1 +; ILP32-ILP32F-WITHFP-NEXT: addi sp, s0, -16 +; ILP32-ILP32F-WITHFP-NEXT: lw s1, 4(sp) +; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) +; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) +; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48 +; ILP32-ILP32F-WITHFP-NEXT: ret +; +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va1_va_arg_alloca: +; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw ra, 12(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw s0, 8(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw s1, 4(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi s0, sp, 16 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv s1, a1 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 28(s0) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 24(s0) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 20(s0) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 16(s0) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 12(s0) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 8(s0) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, s0, 8 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, -16(s0) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 4(s0) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a1, 15 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -16 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sub a0, sp, a0 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv sp, a0 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call notdead +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a0, s1 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, s0, -16 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw s1, 4(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw s0, 8(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 12(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 48 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret +; +; LP64-LP64F-LP64D-FPELIM-LABEL: va1_va_arg_alloca: +; LP64-LP64F-LP64D-FPELIM: # %bb.0: +; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -96 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd ra, 24(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd s0, 16(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd s1, 8(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: addi s0, sp, 32 +; LP64-LP64F-LP64D-FPELIM-NEXT: mv s1, a1 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a7, 56(s0) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a6, 48(s0) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 40(s0) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 32(s0) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 24(s0) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 16(s0) +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, s0, 8 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 8 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, -32(s0) +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 1 +; LP64-LP64F-LP64D-FPELIM-NEXT: slli a0, a0, 33 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, -16 +; LP64-LP64F-LP64D-FPELIM-NEXT: slli a1, a1, 32 +; LP64-LP64F-LP64D-FPELIM-NEXT: srli a1, a1, 32 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, a1, 15 +; LP64-LP64F-LP64D-FPELIM-NEXT: and a0, a1, a0 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd s1, 8(s0) +; LP64-LP64F-LP64D-FPELIM-NEXT: sub a0, sp, a0 +; LP64-LP64F-LP64D-FPELIM-NEXT: mv sp, a0 +; LP64-LP64F-LP64D-FPELIM-NEXT: call notdead +; LP64-LP64F-LP64D-FPELIM-NEXT: mv a0, s1 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, s0, -32 +; LP64-LP64F-LP64D-FPELIM-NEXT: ld s1, 8(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: ld s0, 16(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: ld ra, 24(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 96 +; LP64-LP64F-LP64D-FPELIM-NEXT: ret +; +; LP64-LP64F-LP64D-WITHFP-LABEL: va1_va_arg_alloca: +; LP64-LP64F-LP64D-WITHFP: # %bb.0: +; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -96 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd s1, 8(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32 +; LP64-LP64F-LP64D-WITHFP-NEXT: mv s1, a1 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 8 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 8 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -32(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 1 +; LP64-LP64F-LP64D-WITHFP-NEXT: slli a0, a0, 33 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, -16 +; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a1, 32 +; LP64-LP64F-LP64D-WITHFP-NEXT: srli a1, a1, 32 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, a1, 15 +; LP64-LP64F-LP64D-WITHFP-NEXT: and a0, a1, a0 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd s1, 8(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sub a0, sp, a0 +; LP64-LP64F-LP64D-WITHFP-NEXT: mv sp, a0 +; LP64-LP64F-LP64D-WITHFP-NEXT: call notdead +; LP64-LP64F-LP64D-WITHFP-NEXT: mv a0, s1 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, s0, -32 +; LP64-LP64F-LP64D-WITHFP-NEXT: ld s1, 8(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 96 +; LP64-LP64F-LP64D-WITHFP-NEXT: ret %va = alloca i8*, align 4 %1 = bitcast i8** %va to i8* call void @llvm.va_start(i8* %1) @@ -181,32 +405,71 @@ define i32 @va1_va_arg_alloca(i8* %fmt, ...) nounwind { define void @va1_caller() nounwind { ; Pass a double, as a float would be promoted by a C/C++ frontend -; RV32I-FPELIM-LABEL: va1_caller: -; RV32I-FPELIM: # %bb.0: -; RV32I-FPELIM-NEXT: addi sp, sp, -16 -; RV32I-FPELIM-NEXT: sw ra, 12(sp) -; RV32I-FPELIM-NEXT: mv a2, zero -; RV32I-FPELIM-NEXT: lui a3, 261888 -; RV32I-FPELIM-NEXT: addi a4, zero, 2 -; RV32I-FPELIM-NEXT: call va1 -; RV32I-FPELIM-NEXT: lw ra, 12(sp) -; RV32I-FPELIM-NEXT: addi sp, sp, 16 -; RV32I-FPELIM-NEXT: ret +; ILP32-ILP32F-FPELIM-LABEL: va1_caller: +; ILP32-ILP32F-FPELIM: # %bb.0: +; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -16 +; ILP32-ILP32F-FPELIM-NEXT: sw ra, 12(sp) +; ILP32-ILP32F-FPELIM-NEXT: mv a2, zero +; ILP32-ILP32F-FPELIM-NEXT: lui a3, 261888 +; ILP32-ILP32F-FPELIM-NEXT: addi a4, zero, 2 +; ILP32-ILP32F-FPELIM-NEXT: call va1 +; ILP32-ILP32F-FPELIM-NEXT: lw ra, 12(sp) +; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 16 +; ILP32-ILP32F-FPELIM-NEXT: ret ; -; RV32I-WITHFP-LABEL: va1_caller: -; RV32I-WITHFP: # %bb.0: -; RV32I-WITHFP-NEXT: addi sp, sp, -16 -; RV32I-WITHFP-NEXT: sw ra, 12(sp) -; RV32I-WITHFP-NEXT: sw s0, 8(sp) -; RV32I-WITHFP-NEXT: addi s0, sp, 16 -; RV32I-WITHFP-NEXT: mv a2, zero -; RV32I-WITHFP-NEXT: lui a3, 261888 -; RV32I-WITHFP-NEXT: addi a4, zero, 2 -; RV32I-WITHFP-NEXT: call va1 -; RV32I-WITHFP-NEXT: lw s0, 8(sp) -; RV32I-WITHFP-NEXT: lw ra, 12(sp) -; RV32I-WITHFP-NEXT: addi sp, sp, 16 -; RV32I-WITHFP-NEXT: ret +; ILP32-ILP32F-WITHFP-LABEL: va1_caller: +; ILP32-ILP32F-WITHFP: # %bb.0: +; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -16 +; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp) +; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) +; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16 +; ILP32-ILP32F-WITHFP-NEXT: mv a2, zero +; ILP32-ILP32F-WITHFP-NEXT: lui a3, 261888 +; ILP32-ILP32F-WITHFP-NEXT: addi a4, zero, 2 +; ILP32-ILP32F-WITHFP-NEXT: call va1 +; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) +; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) +; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 16 +; ILP32-ILP32F-WITHFP-NEXT: ret +; +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va1_caller: +; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -16 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw ra, 12(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a2, zero +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a3, 261888 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a4, zero, 2 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call va1 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 12(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 16 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret +; +; LP64-LP64F-LP64D-FPELIM-LABEL: va1_caller: +; LP64-LP64F-LP64D-FPELIM: # %bb.0: +; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -16 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd ra, 8(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 1023 +; LP64-LP64F-LP64D-FPELIM-NEXT: slli a1, a0, 52 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a2, zero, 2 +; LP64-LP64F-LP64D-FPELIM-NEXT: call va1 +; LP64-LP64F-LP64D-FPELIM-NEXT: ld ra, 8(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 16 +; LP64-LP64F-LP64D-FPELIM-NEXT: ret +; +; LP64-LP64F-LP64D-WITHFP-LABEL: va1_caller: +; LP64-LP64F-LP64D-WITHFP: # %bb.0: +; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -16 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 8(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 0(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 16 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 1023 +; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a0, 52 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a2, zero, 2 +; LP64-LP64F-LP64D-WITHFP-NEXT: call va1 +; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 0(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 8(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 16 +; LP64-LP64F-LP64D-WITHFP-NEXT: ret %1 = call i32 (i8*, ...) @va1(i8* undef, double 1.0, i32 2) ret void } @@ -215,50 +478,127 @@ define void @va1_caller() nounwind { ; register pair (where the first register is even-numbered). define i64 @va2(i8 *%fmt, ...) nounwind { -; RV32I-FPELIM-LABEL: va2: -; RV32I-FPELIM: # %bb.0: -; RV32I-FPELIM-NEXT: addi sp, sp, -48 -; RV32I-FPELIM-NEXT: sw a7, 44(sp) -; RV32I-FPELIM-NEXT: sw a6, 40(sp) -; RV32I-FPELIM-NEXT: sw a5, 36(sp) -; RV32I-FPELIM-NEXT: sw a4, 32(sp) -; RV32I-FPELIM-NEXT: sw a3, 28(sp) -; RV32I-FPELIM-NEXT: sw a2, 24(sp) -; RV32I-FPELIM-NEXT: sw a1, 20(sp) -; RV32I-FPELIM-NEXT: addi a0, sp, 35 -; RV32I-FPELIM-NEXT: sw a0, 12(sp) -; RV32I-FPELIM-NEXT: addi a0, sp, 27 -; RV32I-FPELIM-NEXT: andi a1, a0, -8 -; RV32I-FPELIM-NEXT: lw a0, 0(a1) -; RV32I-FPELIM-NEXT: ori a1, a1, 4 -; RV32I-FPELIM-NEXT: lw a1, 0(a1) -; RV32I-FPELIM-NEXT: addi sp, sp, 48 -; RV32I-FPELIM-NEXT: ret +; ILP32-ILP32F-FPELIM-LABEL: va2: +; ILP32-ILP32F-FPELIM: # %bb.0: +; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -48 +; ILP32-ILP32F-FPELIM-NEXT: sw a7, 44(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a6, 40(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a5, 36(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a4, 32(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a3, 28(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a2, 24(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a1, 20(sp) +; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 35 +; ILP32-ILP32F-FPELIM-NEXT: sw a0, 12(sp) +; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 27 +; ILP32-ILP32F-FPELIM-NEXT: andi a1, a0, -8 +; ILP32-ILP32F-FPELIM-NEXT: lw a0, 0(a1) +; ILP32-ILP32F-FPELIM-NEXT: ori a1, a1, 4 +; ILP32-ILP32F-FPELIM-NEXT: lw a1, 0(a1) +; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48 +; ILP32-ILP32F-FPELIM-NEXT: ret ; -; RV32I-WITHFP-LABEL: va2: -; RV32I-WITHFP: # %bb.0: -; RV32I-WITHFP-NEXT: addi sp, sp, -48 -; RV32I-WITHFP-NEXT: sw ra, 12(sp) -; RV32I-WITHFP-NEXT: sw s0, 8(sp) -; RV32I-WITHFP-NEXT: addi s0, sp, 16 -; RV32I-WITHFP-NEXT: sw a7, 28(s0) -; RV32I-WITHFP-NEXT: sw a6, 24(s0) -; RV32I-WITHFP-NEXT: sw a5, 20(s0) -; RV32I-WITHFP-NEXT: sw a4, 16(s0) -; RV32I-WITHFP-NEXT: sw a3, 12(s0) -; RV32I-WITHFP-NEXT: sw a2, 8(s0) -; RV32I-WITHFP-NEXT: sw a1, 4(s0) -; RV32I-WITHFP-NEXT: addi a0, s0, 19 -; RV32I-WITHFP-NEXT: sw a0, -12(s0) -; RV32I-WITHFP-NEXT: addi a0, s0, 11 -; RV32I-WITHFP-NEXT: andi a1, a0, -8 -; RV32I-WITHFP-NEXT: lw a0, 0(a1) -; RV32I-WITHFP-NEXT: ori a1, a1, 4 -; RV32I-WITHFP-NEXT: lw a1, 0(a1) -; RV32I-WITHFP-NEXT: lw s0, 8(sp) -; RV32I-WITHFP-NEXT: lw ra, 12(sp) -; RV32I-WITHFP-NEXT: addi sp, sp, 48 -; RV32I-WITHFP-NEXT: ret +; ILP32-ILP32F-WITHFP-LABEL: va2: +; ILP32-ILP32F-WITHFP: # %bb.0: +; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48 +; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp) +; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) +; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16 +; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0) +; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 19 +; ILP32-ILP32F-WITHFP-NEXT: sw a0, -12(s0) +; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 11 +; ILP32-ILP32F-WITHFP-NEXT: andi a1, a0, -8 +; ILP32-ILP32F-WITHFP-NEXT: lw a0, 0(a1) +; ILP32-ILP32F-WITHFP-NEXT: ori a1, a1, 4 +; ILP32-ILP32F-WITHFP-NEXT: lw a1, 0(a1) +; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) +; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) +; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48 +; ILP32-ILP32F-WITHFP-NEXT: ret +; +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va2: +; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 44(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 36(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 32(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 28(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 24(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 20(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 35 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 12(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 27 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a1, a0, -8 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a0, 0(a1) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ori a1, a1, 4 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a1, 0(a1) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 48 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret +; +; LP64-LP64F-LP64D-FPELIM-LABEL: va2: +; LP64-LP64F-LP64D-FPELIM: # %bb.0: +; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -80 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, sp, 24 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a7, 72(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a6, 64(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 56(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 48(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 40(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 32(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 24(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: lw a0, 8(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 7 +; LP64-LP64F-LP64D-FPELIM-NEXT: slli a1, a0, 32 +; LP64-LP64F-LP64D-FPELIM-NEXT: srli a1, a1, 32 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, a1, 8 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 8(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, zero, 1 +; LP64-LP64F-LP64D-FPELIM-NEXT: slli a1, a1, 32 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, a1, -8 +; LP64-LP64F-LP64D-FPELIM-NEXT: and a0, a0, a1 +; LP64-LP64F-LP64D-FPELIM-NEXT: ld a0, 0(a0) +; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 80 +; LP64-LP64F-LP64D-FPELIM-NEXT: ret +; +; LP64-LP64F-LP64D-WITHFP-LABEL: va2: +; LP64-LP64F-LP64D-WITHFP: # %bb.0: +; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -96 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 8 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -24(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: lw a0, -24(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 7 +; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a0, 32 +; LP64-LP64F-LP64D-WITHFP-NEXT: srli a1, a1, 32 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, a1, 8 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, -24(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, zero, 1 +; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a1, 32 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, a1, -8 +; LP64-LP64F-LP64D-WITHFP-NEXT: and a0, a0, a1 +; LP64-LP64F-LP64D-WITHFP-NEXT: ld a0, 0(a0) +; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 96 +; LP64-LP64F-LP64D-WITHFP-NEXT: ret %va = alloca i8*, align 4 %1 = bitcast i8** %va to i8* call void @llvm.va_start(i8* %1) @@ -277,52 +617,112 @@ define i64 @va2(i8 *%fmt, ...) nounwind { } define i64 @va2_va_arg(i8 *%fmt, ...) nounwind { -; RV32I-FPELIM-LABEL: va2_va_arg: -; RV32I-FPELIM: # %bb.0: -; RV32I-FPELIM-NEXT: addi sp, sp, -48 -; RV32I-FPELIM-NEXT: sw a7, 44(sp) -; RV32I-FPELIM-NEXT: sw a6, 40(sp) -; RV32I-FPELIM-NEXT: sw a5, 36(sp) -; RV32I-FPELIM-NEXT: sw a4, 32(sp) -; RV32I-FPELIM-NEXT: sw a3, 28(sp) -; RV32I-FPELIM-NEXT: sw a2, 24(sp) -; RV32I-FPELIM-NEXT: sw a1, 20(sp) -; RV32I-FPELIM-NEXT: addi a0, sp, 27 -; RV32I-FPELIM-NEXT: andi a0, a0, -8 -; RV32I-FPELIM-NEXT: ori a1, a0, 4 -; RV32I-FPELIM-NEXT: sw a1, 12(sp) -; RV32I-FPELIM-NEXT: lw a0, 0(a0) -; RV32I-FPELIM-NEXT: addi a2, a1, 4 -; RV32I-FPELIM-NEXT: sw a2, 12(sp) -; RV32I-FPELIM-NEXT: lw a1, 0(a1) -; RV32I-FPELIM-NEXT: addi sp, sp, 48 -; RV32I-FPELIM-NEXT: ret +; ILP32-ILP32F-FPELIM-LABEL: va2_va_arg: +; ILP32-ILP32F-FPELIM: # %bb.0: +; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -48 +; ILP32-ILP32F-FPELIM-NEXT: sw a7, 44(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a6, 40(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a5, 36(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a4, 32(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a3, 28(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a2, 24(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a1, 20(sp) +; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 27 +; ILP32-ILP32F-FPELIM-NEXT: andi a0, a0, -8 +; ILP32-ILP32F-FPELIM-NEXT: ori a1, a0, 4 +; ILP32-ILP32F-FPELIM-NEXT: sw a1, 12(sp) +; ILP32-ILP32F-FPELIM-NEXT: lw a0, 0(a0) +; ILP32-ILP32F-FPELIM-NEXT: addi a2, a1, 4 +; ILP32-ILP32F-FPELIM-NEXT: sw a2, 12(sp) +; ILP32-ILP32F-FPELIM-NEXT: lw a1, 0(a1) +; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48 +; ILP32-ILP32F-FPELIM-NEXT: ret ; -; RV32I-WITHFP-LABEL: va2_va_arg: -; RV32I-WITHFP: # %bb.0: -; RV32I-WITHFP-NEXT: addi sp, sp, -48 -; RV32I-WITHFP-NEXT: sw ra, 12(sp) -; RV32I-WITHFP-NEXT: sw s0, 8(sp) -; RV32I-WITHFP-NEXT: addi s0, sp, 16 -; RV32I-WITHFP-NEXT: sw a7, 28(s0) -; RV32I-WITHFP-NEXT: sw a6, 24(s0) -; RV32I-WITHFP-NEXT: sw a5, 20(s0) -; RV32I-WITHFP-NEXT: sw a4, 16(s0) -; RV32I-WITHFP-NEXT: sw a3, 12(s0) -; RV32I-WITHFP-NEXT: sw a2, 8(s0) -; RV32I-WITHFP-NEXT: sw a1, 4(s0) -; RV32I-WITHFP-NEXT: addi a0, s0, 11 -; RV32I-WITHFP-NEXT: andi a0, a0, -8 -; RV32I-WITHFP-NEXT: ori a1, a0, 4 -; RV32I-WITHFP-NEXT: sw a1, -12(s0) -; RV32I-WITHFP-NEXT: lw a0, 0(a0) -; RV32I-WITHFP-NEXT: addi a2, a1, 4 -; RV32I-WITHFP-NEXT: sw a2, -12(s0) -; RV32I-WITHFP-NEXT: lw a1, 0(a1) -; RV32I-WITHFP-NEXT: lw s0, 8(sp) -; RV32I-WITHFP-NEXT: lw ra, 12(sp) -; RV32I-WITHFP-NEXT: addi sp, sp, 48 -; RV32I-WITHFP-NEXT: ret +; ILP32-ILP32F-WITHFP-LABEL: va2_va_arg: +; ILP32-ILP32F-WITHFP: # %bb.0: +; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48 +; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp) +; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) +; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16 +; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0) +; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 11 +; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -8 +; ILP32-ILP32F-WITHFP-NEXT: ori a1, a0, 4 +; ILP32-ILP32F-WITHFP-NEXT: sw a1, -12(s0) +; ILP32-ILP32F-WITHFP-NEXT: lw a0, 0(a0) +; ILP32-ILP32F-WITHFP-NEXT: addi a2, a1, 4 +; ILP32-ILP32F-WITHFP-NEXT: sw a2, -12(s0) +; ILP32-ILP32F-WITHFP-NEXT: lw a1, 0(a1) +; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) +; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) +; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48 +; ILP32-ILP32F-WITHFP-NEXT: ret +; +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va2_va_arg: +; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 44(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 36(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 32(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 28(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 24(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 20(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 27 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -8 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, a0, 8 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 12(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: fld ft0, 0(a0) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: fsd ft0, 0(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a0, 0(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a1, 4(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 48 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret +; +; LP64-LP64F-LP64D-FPELIM-LABEL: va2_va_arg: +; LP64-LP64F-LP64D-FPELIM: # %bb.0: +; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -80 +; LP64-LP64F-LP64D-FPELIM-NEXT: mv a0, a1 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a7, 72(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a6, 64(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 56(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 48(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 40(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 32(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, sp, 24 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, a1, 8 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 8(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 24(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 80 +; LP64-LP64F-LP64D-FPELIM-NEXT: ret +; +; LP64-LP64F-LP64D-WITHFP-LABEL: va2_va_arg: +; LP64-LP64F-LP64D-WITHFP: # %bb.0: +; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -96 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32 +; LP64-LP64F-LP64D-WITHFP-NEXT: mv a0, a1 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, s0, 8 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, a1, 8 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, -24(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, 8(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 96 +; LP64-LP64F-LP64D-WITHFP-NEXT: ret %va = alloca i8*, align 4 %1 = bitcast i8** %va to i8* call void @llvm.va_start(i8* %1) @@ -333,30 +733,66 @@ define i64 @va2_va_arg(i8 *%fmt, ...) nounwind { } define void @va2_caller() nounwind { -; RV32I-FPELIM-LABEL: va2_caller: -; RV32I-FPELIM: # %bb.0: -; RV32I-FPELIM-NEXT: addi sp, sp, -16 -; RV32I-FPELIM-NEXT: sw ra, 12(sp) -; RV32I-FPELIM-NEXT: mv a2, zero -; RV32I-FPELIM-NEXT: lui a3, 261888 -; RV32I-FPELIM-NEXT: call va2 -; RV32I-FPELIM-NEXT: lw ra, 12(sp) -; RV32I-FPELIM-NEXT: addi sp, sp, 16 -; RV32I-FPELIM-NEXT: ret +; ILP32-ILP32F-FPELIM-LABEL: va2_caller: +; ILP32-ILP32F-FPELIM: # %bb.0: +; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -16 +; ILP32-ILP32F-FPELIM-NEXT: sw ra, 12(sp) +; ILP32-ILP32F-FPELIM-NEXT: mv a2, zero +; ILP32-ILP32F-FPELIM-NEXT: lui a3, 261888 +; ILP32-ILP32F-FPELIM-NEXT: call va2 +; ILP32-ILP32F-FPELIM-NEXT: lw ra, 12(sp) +; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 16 +; ILP32-ILP32F-FPELIM-NEXT: ret ; -; RV32I-WITHFP-LABEL: va2_caller: -; RV32I-WITHFP: # %bb.0: -; RV32I-WITHFP-NEXT: addi sp, sp, -16 -; RV32I-WITHFP-NEXT: sw ra, 12(sp) -; RV32I-WITHFP-NEXT: sw s0, 8(sp) -; RV32I-WITHFP-NEXT: addi s0, sp, 16 -; RV32I-WITHFP-NEXT: mv a2, zero -; RV32I-WITHFP-NEXT: lui a3, 261888 -; RV32I-WITHFP-NEXT: call va2 -; RV32I-WITHFP-NEXT: lw s0, 8(sp) -; RV32I-WITHFP-NEXT: lw ra, 12(sp) -; RV32I-WITHFP-NEXT: addi sp, sp, 16 -; RV32I-WITHFP-NEXT: ret +; ILP32-ILP32F-WITHFP-LABEL: va2_caller: +; ILP32-ILP32F-WITHFP: # %bb.0: +; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -16 +; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp) +; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) +; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16 +; ILP32-ILP32F-WITHFP-NEXT: mv a2, zero +; ILP32-ILP32F-WITHFP-NEXT: lui a3, 261888 +; ILP32-ILP32F-WITHFP-NEXT: call va2 +; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) +; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) +; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 16 +; ILP32-ILP32F-WITHFP-NEXT: ret +; +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va2_caller: +; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -16 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw ra, 12(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a2, zero +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a3, 261888 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call va2 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 12(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 16 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret +; +; LP64-LP64F-LP64D-FPELIM-LABEL: va2_caller: +; LP64-LP64F-LP64D-FPELIM: # %bb.0: +; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -16 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd ra, 8(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 1023 +; LP64-LP64F-LP64D-FPELIM-NEXT: slli a1, a0, 52 +; LP64-LP64F-LP64D-FPELIM-NEXT: call va2 +; LP64-LP64F-LP64D-FPELIM-NEXT: ld ra, 8(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 16 +; LP64-LP64F-LP64D-FPELIM-NEXT: ret +; +; LP64-LP64F-LP64D-WITHFP-LABEL: va2_caller: +; LP64-LP64F-LP64D-WITHFP: # %bb.0: +; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -16 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 8(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 0(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 16 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 1023 +; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a0, 52 +; LP64-LP64F-LP64D-WITHFP-NEXT: call va2 +; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 0(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 8(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 16 +; LP64-LP64F-LP64D-WITHFP-NEXT: ret %1 = call i64 (i8*, ...) @va2(i8* undef, double 1.000000e+00) ret void } @@ -365,54 +801,133 @@ define void @va2_caller() nounwind { ; vararg double is passed in a4 and a5 (rather than a3 and a4) define i64 @va3(i32 %a, i64 %b, ...) nounwind { -; RV32I-FPELIM-LABEL: va3: -; RV32I-FPELIM: # %bb.0: -; RV32I-FPELIM-NEXT: addi sp, sp, -32 -; RV32I-FPELIM-NEXT: sw a7, 28(sp) -; RV32I-FPELIM-NEXT: sw a6, 24(sp) -; RV32I-FPELIM-NEXT: sw a5, 20(sp) -; RV32I-FPELIM-NEXT: sw a4, 16(sp) -; RV32I-FPELIM-NEXT: sw a3, 12(sp) -; RV32I-FPELIM-NEXT: addi a0, sp, 27 -; RV32I-FPELIM-NEXT: sw a0, 4(sp) -; RV32I-FPELIM-NEXT: addi a0, sp, 19 -; RV32I-FPELIM-NEXT: andi a0, a0, -8 -; RV32I-FPELIM-NEXT: ori a3, a0, 4 -; RV32I-FPELIM-NEXT: lw a3, 0(a3) -; RV32I-FPELIM-NEXT: add a2, a2, a3 -; RV32I-FPELIM-NEXT: lw a0, 0(a0) -; RV32I-FPELIM-NEXT: add a0, a1, a0 -; RV32I-FPELIM-NEXT: sltu a1, a0, a1 -; RV32I-FPELIM-NEXT: add a1, a2, a1 -; RV32I-FPELIM-NEXT: addi sp, sp, 32 -; RV32I-FPELIM-NEXT: ret +; ILP32-ILP32F-FPELIM-LABEL: va3: +; ILP32-ILP32F-FPELIM: # %bb.0: +; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -32 +; ILP32-ILP32F-FPELIM-NEXT: sw a7, 28(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a6, 24(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a5, 20(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a4, 16(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a3, 12(sp) +; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 27 +; ILP32-ILP32F-FPELIM-NEXT: sw a0, 4(sp) +; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 19 +; ILP32-ILP32F-FPELIM-NEXT: andi a0, a0, -8 +; ILP32-ILP32F-FPELIM-NEXT: ori a3, a0, 4 +; ILP32-ILP32F-FPELIM-NEXT: lw a3, 0(a3) +; ILP32-ILP32F-FPELIM-NEXT: add a2, a2, a3 +; ILP32-ILP32F-FPELIM-NEXT: lw a0, 0(a0) +; ILP32-ILP32F-FPELIM-NEXT: add a0, a1, a0 +; ILP32-ILP32F-FPELIM-NEXT: sltu a1, a0, a1 +; ILP32-ILP32F-FPELIM-NEXT: add a1, a2, a1 +; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 32 +; ILP32-ILP32F-FPELIM-NEXT: ret ; -; RV32I-WITHFP-LABEL: va3: -; RV32I-WITHFP: # %bb.0: -; RV32I-WITHFP-NEXT: addi sp, sp, -48 -; RV32I-WITHFP-NEXT: sw ra, 20(sp) -; RV32I-WITHFP-NEXT: sw s0, 16(sp) -; RV32I-WITHFP-NEXT: addi s0, sp, 24 -; RV32I-WITHFP-NEXT: sw a7, 20(s0) -; RV32I-WITHFP-NEXT: sw a6, 16(s0) -; RV32I-WITHFP-NEXT: sw a5, 12(s0) -; RV32I-WITHFP-NEXT: sw a4, 8(s0) -; RV32I-WITHFP-NEXT: sw a3, 4(s0) -; RV32I-WITHFP-NEXT: addi a0, s0, 19 -; RV32I-WITHFP-NEXT: sw a0, -12(s0) -; RV32I-WITHFP-NEXT: addi a0, s0, 11 -; RV32I-WITHFP-NEXT: andi a0, a0, -8 -; RV32I-WITHFP-NEXT: ori a3, a0, 4 -; RV32I-WITHFP-NEXT: lw a3, 0(a3) -; RV32I-WITHFP-NEXT: add a2, a2, a3 -; RV32I-WITHFP-NEXT: lw a0, 0(a0) -; RV32I-WITHFP-NEXT: add a0, a1, a0 -; RV32I-WITHFP-NEXT: sltu a1, a0, a1 -; RV32I-WITHFP-NEXT: add a1, a2, a1 -; RV32I-WITHFP-NEXT: lw s0, 16(sp) -; RV32I-WITHFP-NEXT: lw ra, 20(sp) -; RV32I-WITHFP-NEXT: addi sp, sp, 48 -; RV32I-WITHFP-NEXT: ret +; ILP32-ILP32F-WITHFP-LABEL: va3: +; ILP32-ILP32F-WITHFP: # %bb.0: +; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48 +; ILP32-ILP32F-WITHFP-NEXT: sw ra, 20(sp) +; ILP32-ILP32F-WITHFP-NEXT: sw s0, 16(sp) +; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 24 +; ILP32-ILP32F-WITHFP-NEXT: sw a7, 20(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a6, 16(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a5, 12(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a4, 8(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a3, 4(s0) +; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 19 +; ILP32-ILP32F-WITHFP-NEXT: sw a0, -12(s0) +; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 11 +; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -8 +; ILP32-ILP32F-WITHFP-NEXT: ori a3, a0, 4 +; ILP32-ILP32F-WITHFP-NEXT: lw a3, 0(a3) +; ILP32-ILP32F-WITHFP-NEXT: add a2, a2, a3 +; ILP32-ILP32F-WITHFP-NEXT: lw a0, 0(a0) +; ILP32-ILP32F-WITHFP-NEXT: add a0, a1, a0 +; ILP32-ILP32F-WITHFP-NEXT: sltu a1, a0, a1 +; ILP32-ILP32F-WITHFP-NEXT: add a1, a2, a1 +; ILP32-ILP32F-WITHFP-NEXT: lw s0, 16(sp) +; ILP32-ILP32F-WITHFP-NEXT: lw ra, 20(sp) +; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48 +; ILP32-ILP32F-WITHFP-NEXT: ret +; +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va3: +; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -32 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 28(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 24(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 20(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 16(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 12(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 27 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 4(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 19 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -8 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ori a3, a0, 4 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a3, 0(a3) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a2, a2, a3 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a0, 0(a0) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a0, a1, a0 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sltu a1, a0, a1 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a1, a2, a1 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 32 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret +; +; LP64-LP64F-LP64D-FPELIM-LABEL: va3: +; LP64-LP64F-LP64D-FPELIM: # %bb.0: +; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -64 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, sp, 16 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a7, 56(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a6, 48(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 40(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 32(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 24(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 16(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: lw a0, 8(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 7 +; LP64-LP64F-LP64D-FPELIM-NEXT: slli a2, a0, 32 +; LP64-LP64F-LP64D-FPELIM-NEXT: srli a2, a2, 32 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a2, a2, 8 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 8(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a2, zero, 1 +; LP64-LP64F-LP64D-FPELIM-NEXT: slli a2, a2, 32 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a2, a2, -8 +; LP64-LP64F-LP64D-FPELIM-NEXT: and a0, a0, a2 +; LP64-LP64F-LP64D-FPELIM-NEXT: ld a0, 0(a0) +; LP64-LP64F-LP64D-FPELIM-NEXT: add a0, a1, a0 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 64 +; LP64-LP64F-LP64D-FPELIM-NEXT: ret +; +; LP64-LP64F-LP64D-WITHFP-LABEL: va3: +; LP64-LP64F-LP64D-WITHFP: # %bb.0: +; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -80 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32 +; LP64-LP64F-LP64D-WITHFP-NEXT: mv a0, s0 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -24(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 40(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 32(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 24(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 16(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 8(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 0(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: lw a0, -24(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 7 +; LP64-LP64F-LP64D-WITHFP-NEXT: slli a2, a0, 32 +; LP64-LP64F-LP64D-WITHFP-NEXT: srli a2, a2, 32 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a2, a2, 8 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, -24(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a2, zero, 1 +; LP64-LP64F-LP64D-WITHFP-NEXT: slli a2, a2, 32 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a2, a2, -8 +; LP64-LP64F-LP64D-WITHFP-NEXT: and a0, a0, a2 +; LP64-LP64F-LP64D-WITHFP-NEXT: ld a0, 0(a0) +; LP64-LP64F-LP64D-WITHFP-NEXT: add a0, a1, a0 +; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 80 +; LP64-LP64F-LP64D-WITHFP-NEXT: ret %va = alloca i8*, align 4 %1 = bitcast i8** %va to i8* call void @llvm.va_start(i8* %1) @@ -432,56 +947,116 @@ define i64 @va3(i32 %a, i64 %b, ...) nounwind { } define i64 @va3_va_arg(i32 %a, i64 %b, ...) nounwind { -; RV32I-FPELIM-LABEL: va3_va_arg: -; RV32I-FPELIM: # %bb.0: -; RV32I-FPELIM-NEXT: addi sp, sp, -32 -; RV32I-FPELIM-NEXT: sw a7, 28(sp) -; RV32I-FPELIM-NEXT: sw a6, 24(sp) -; RV32I-FPELIM-NEXT: sw a5, 20(sp) -; RV32I-FPELIM-NEXT: sw a4, 16(sp) -; RV32I-FPELIM-NEXT: sw a3, 12(sp) -; RV32I-FPELIM-NEXT: addi a0, sp, 19 -; RV32I-FPELIM-NEXT: andi a0, a0, -8 -; RV32I-FPELIM-NEXT: ori a3, a0, 4 -; RV32I-FPELIM-NEXT: sw a3, 4(sp) -; RV32I-FPELIM-NEXT: lw a0, 0(a0) -; RV32I-FPELIM-NEXT: addi a4, a3, 4 -; RV32I-FPELIM-NEXT: sw a4, 4(sp) -; RV32I-FPELIM-NEXT: lw a3, 0(a3) -; RV32I-FPELIM-NEXT: add a2, a2, a3 -; RV32I-FPELIM-NEXT: add a0, a1, a0 -; RV32I-FPELIM-NEXT: sltu a1, a0, a1 -; RV32I-FPELIM-NEXT: add a1, a2, a1 -; RV32I-FPELIM-NEXT: addi sp, sp, 32 -; RV32I-FPELIM-NEXT: ret +; ILP32-ILP32F-FPELIM-LABEL: va3_va_arg: +; ILP32-ILP32F-FPELIM: # %bb.0: +; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -32 +; ILP32-ILP32F-FPELIM-NEXT: sw a7, 28(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a6, 24(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a5, 20(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a4, 16(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a3, 12(sp) +; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 19 +; ILP32-ILP32F-FPELIM-NEXT: andi a0, a0, -8 +; ILP32-ILP32F-FPELIM-NEXT: ori a3, a0, 4 +; ILP32-ILP32F-FPELIM-NEXT: sw a3, 4(sp) +; ILP32-ILP32F-FPELIM-NEXT: lw a0, 0(a0) +; ILP32-ILP32F-FPELIM-NEXT: addi a4, a3, 4 +; ILP32-ILP32F-FPELIM-NEXT: sw a4, 4(sp) +; ILP32-ILP32F-FPELIM-NEXT: lw a3, 0(a3) +; ILP32-ILP32F-FPELIM-NEXT: add a2, a2, a3 +; ILP32-ILP32F-FPELIM-NEXT: add a0, a1, a0 +; ILP32-ILP32F-FPELIM-NEXT: sltu a1, a0, a1 +; ILP32-ILP32F-FPELIM-NEXT: add a1, a2, a1 +; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 32 +; ILP32-ILP32F-FPELIM-NEXT: ret ; -; RV32I-WITHFP-LABEL: va3_va_arg: -; RV32I-WITHFP: # %bb.0: -; RV32I-WITHFP-NEXT: addi sp, sp, -48 -; RV32I-WITHFP-NEXT: sw ra, 20(sp) -; RV32I-WITHFP-NEXT: sw s0, 16(sp) -; RV32I-WITHFP-NEXT: addi s0, sp, 24 -; RV32I-WITHFP-NEXT: sw a7, 20(s0) -; RV32I-WITHFP-NEXT: sw a6, 16(s0) -; RV32I-WITHFP-NEXT: sw a5, 12(s0) -; RV32I-WITHFP-NEXT: sw a4, 8(s0) -; RV32I-WITHFP-NEXT: sw a3, 4(s0) -; RV32I-WITHFP-NEXT: addi a0, s0, 11 -; RV32I-WITHFP-NEXT: andi a0, a0, -8 -; RV32I-WITHFP-NEXT: ori a3, a0, 4 -; RV32I-WITHFP-NEXT: sw a3, -12(s0) -; RV32I-WITHFP-NEXT: lw a0, 0(a0) -; RV32I-WITHFP-NEXT: addi a4, a3, 4 -; RV32I-WITHFP-NEXT: sw a4, -12(s0) -; RV32I-WITHFP-NEXT: lw a3, 0(a3) -; RV32I-WITHFP-NEXT: add a2, a2, a3 -; RV32I-WITHFP-NEXT: add a0, a1, a0 -; RV32I-WITHFP-NEXT: sltu a1, a0, a1 -; RV32I-WITHFP-NEXT: add a1, a2, a1 -; RV32I-WITHFP-NEXT: lw s0, 16(sp) -; RV32I-WITHFP-NEXT: lw ra, 20(sp) -; RV32I-WITHFP-NEXT: addi sp, sp, 48 -; RV32I-WITHFP-NEXT: ret +; ILP32-ILP32F-WITHFP-LABEL: va3_va_arg: +; ILP32-ILP32F-WITHFP: # %bb.0: +; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48 +; ILP32-ILP32F-WITHFP-NEXT: sw ra, 20(sp) +; ILP32-ILP32F-WITHFP-NEXT: sw s0, 16(sp) +; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 24 +; ILP32-ILP32F-WITHFP-NEXT: sw a7, 20(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a6, 16(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a5, 12(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a4, 8(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a3, 4(s0) +; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 11 +; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -8 +; ILP32-ILP32F-WITHFP-NEXT: ori a3, a0, 4 +; ILP32-ILP32F-WITHFP-NEXT: sw a3, -12(s0) +; ILP32-ILP32F-WITHFP-NEXT: lw a0, 0(a0) +; ILP32-ILP32F-WITHFP-NEXT: addi a4, a3, 4 +; ILP32-ILP32F-WITHFP-NEXT: sw a4, -12(s0) +; ILP32-ILP32F-WITHFP-NEXT: lw a3, 0(a3) +; ILP32-ILP32F-WITHFP-NEXT: add a2, a2, a3 +; ILP32-ILP32F-WITHFP-NEXT: add a0, a1, a0 +; ILP32-ILP32F-WITHFP-NEXT: sltu a1, a0, a1 +; ILP32-ILP32F-WITHFP-NEXT: add a1, a2, a1 +; ILP32-ILP32F-WITHFP-NEXT: lw s0, 16(sp) +; ILP32-ILP32F-WITHFP-NEXT: lw ra, 20(sp) +; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48 +; ILP32-ILP32F-WITHFP-NEXT: ret +; +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va3_va_arg: +; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 44(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 36(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 32(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 28(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 35 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -8 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a3, a0, 8 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 20(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: fld ft0, 0(a0) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: fsd ft0, 8(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a0, 12(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a2, a2, a0 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a0, 8(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a0, a1, a0 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sltu a1, a0, a1 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a1, a2, a1 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 48 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret +; +; LP64-LP64F-LP64D-FPELIM-LABEL: va3_va_arg: +; LP64-LP64F-LP64D-FPELIM: # %bb.0: +; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -64 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a7, 56(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a6, 48(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 40(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 32(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 24(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, sp, 16 +; LP64-LP64F-LP64D-FPELIM-NEXT: ori a0, a0, 8 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 16(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: add a0, a1, a2 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 64 +; LP64-LP64F-LP64D-FPELIM-NEXT: ret +; +; LP64-LP64F-LP64D-WITHFP-LABEL: va3_va_arg: +; LP64-LP64F-LP64D-WITHFP: # %bb.0: +; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -80 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 40(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 32(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 24(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 16(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 8(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: mv a0, s0 +; LP64-LP64F-LP64D-WITHFP-NEXT: ori a0, a0, 8 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -24(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 0(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: add a0, a1, a2 +; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 80 +; LP64-LP64F-LP64D-WITHFP-NEXT: ret %va = alloca i8*, align 4 %1 = bitcast i8** %va to i8* call void @llvm.va_start(i8* %1) @@ -493,36 +1068,79 @@ define i64 @va3_va_arg(i32 %a, i64 %b, ...) nounwind { } define void @va3_caller() nounwind { -; RV32I-FPELIM-LABEL: va3_caller: -; RV32I-FPELIM: # %bb.0: -; RV32I-FPELIM-NEXT: addi sp, sp, -16 -; RV32I-FPELIM-NEXT: sw ra, 12(sp) -; RV32I-FPELIM-NEXT: addi a0, zero, 2 -; RV32I-FPELIM-NEXT: addi a1, zero, 1111 -; RV32I-FPELIM-NEXT: mv a2, zero -; RV32I-FPELIM-NEXT: mv a4, zero -; RV32I-FPELIM-NEXT: lui a5, 262144 -; RV32I-FPELIM-NEXT: call va3 -; RV32I-FPELIM-NEXT: lw ra, 12(sp) -; RV32I-FPELIM-NEXT: addi sp, sp, 16 -; RV32I-FPELIM-NEXT: ret +; ILP32-ILP32F-FPELIM-LABEL: va3_caller: +; ILP32-ILP32F-FPELIM: # %bb.0: +; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -16 +; ILP32-ILP32F-FPELIM-NEXT: sw ra, 12(sp) +; ILP32-ILP32F-FPELIM-NEXT: addi a0, zero, 2 +; ILP32-ILP32F-FPELIM-NEXT: addi a1, zero, 1111 +; ILP32-ILP32F-FPELIM-NEXT: mv a2, zero +; ILP32-ILP32F-FPELIM-NEXT: mv a4, zero +; ILP32-ILP32F-FPELIM-NEXT: lui a5, 262144 +; ILP32-ILP32F-FPELIM-NEXT: call va3 +; ILP32-ILP32F-FPELIM-NEXT: lw ra, 12(sp) +; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 16 +; ILP32-ILP32F-FPELIM-NEXT: ret ; -; RV32I-WITHFP-LABEL: va3_caller: -; RV32I-WITHFP: # %bb.0: -; RV32I-WITHFP-NEXT: addi sp, sp, -16 -; RV32I-WITHFP-NEXT: sw ra, 12(sp) -; RV32I-WITHFP-NEXT: sw s0, 8(sp) -; RV32I-WITHFP-NEXT: addi s0, sp, 16 -; RV32I-WITHFP-NEXT: addi a0, zero, 2 -; RV32I-WITHFP-NEXT: addi a1, zero, 1111 -; RV32I-WITHFP-NEXT: mv a2, zero -; RV32I-WITHFP-NEXT: mv a4, zero -; RV32I-WITHFP-NEXT: lui a5, 262144 -; RV32I-WITHFP-NEXT: call va3 -; RV32I-WITHFP-NEXT: lw s0, 8(sp) -; RV32I-WITHFP-NEXT: lw ra, 12(sp) -; RV32I-WITHFP-NEXT: addi sp, sp, 16 -; RV32I-WITHFP-NEXT: ret +; ILP32-ILP32F-WITHFP-LABEL: va3_caller: +; ILP32-ILP32F-WITHFP: # %bb.0: +; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -16 +; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp) +; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) +; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16 +; ILP32-ILP32F-WITHFP-NEXT: addi a0, zero, 2 +; ILP32-ILP32F-WITHFP-NEXT: addi a1, zero, 1111 +; ILP32-ILP32F-WITHFP-NEXT: mv a2, zero +; ILP32-ILP32F-WITHFP-NEXT: mv a4, zero +; ILP32-ILP32F-WITHFP-NEXT: lui a5, 262144 +; ILP32-ILP32F-WITHFP-NEXT: call va3 +; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) +; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) +; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 16 +; ILP32-ILP32F-WITHFP-NEXT: ret +; +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va3_caller: +; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -16 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw ra, 12(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, zero, 2 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, zero, 1111 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a2, zero +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a4, zero +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a5, 262144 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call va3 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 12(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 16 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret +; +; LP64-LP64F-LP64D-FPELIM-LABEL: va3_caller: +; LP64-LP64F-LP64D-FPELIM: # %bb.0: +; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -16 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd ra, 8(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 1 +; LP64-LP64F-LP64D-FPELIM-NEXT: slli a2, a0, 62 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 2 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, zero, 1111 +; LP64-LP64F-LP64D-FPELIM-NEXT: call va3 +; LP64-LP64F-LP64D-FPELIM-NEXT: ld ra, 8(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 16 +; LP64-LP64F-LP64D-FPELIM-NEXT: ret +; +; LP64-LP64F-LP64D-WITHFP-LABEL: va3_caller: +; LP64-LP64F-LP64D-WITHFP: # %bb.0: +; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -16 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 8(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 0(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 16 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 1 +; LP64-LP64F-LP64D-WITHFP-NEXT: slli a2, a0, 62 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 2 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, zero, 1111 +; LP64-LP64F-LP64D-WITHFP-NEXT: call va3 +; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 0(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 8(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 16 +; LP64-LP64F-LP64D-WITHFP-NEXT: ret %1 = call i64 (i32, i64, ...) @va3(i32 2, i64 1111, double 2.000000e+00) ret void } @@ -530,90 +1148,218 @@ define void @va3_caller() nounwind { declare void @llvm.va_copy(i8*, i8*) define i32 @va4_va_copy(i32 %argno, ...) nounwind { -; RV32I-FPELIM-LABEL: va4_va_copy: -; RV32I-FPELIM: # %bb.0: -; RV32I-FPELIM-NEXT: addi sp, sp, -48 -; RV32I-FPELIM-NEXT: sw ra, 12(sp) -; RV32I-FPELIM-NEXT: sw s0, 8(sp) -; RV32I-FPELIM-NEXT: mv s0, a1 -; RV32I-FPELIM-NEXT: sw a7, 44(sp) -; RV32I-FPELIM-NEXT: sw a6, 40(sp) -; RV32I-FPELIM-NEXT: sw a5, 36(sp) -; RV32I-FPELIM-NEXT: sw a4, 32(sp) -; RV32I-FPELIM-NEXT: sw a3, 28(sp) -; RV32I-FPELIM-NEXT: sw a2, 24(sp) -; RV32I-FPELIM-NEXT: sw a1, 20(sp) -; RV32I-FPELIM-NEXT: addi a0, sp, 24 -; RV32I-FPELIM-NEXT: sw a0, 4(sp) -; RV32I-FPELIM-NEXT: sw a0, 0(sp) -; RV32I-FPELIM-NEXT: call notdead -; RV32I-FPELIM-NEXT: lw a0, 4(sp) -; RV32I-FPELIM-NEXT: addi a0, a0, 3 -; RV32I-FPELIM-NEXT: andi a0, a0, -4 -; RV32I-FPELIM-NEXT: addi a1, a0, 4 -; RV32I-FPELIM-NEXT: sw a1, 4(sp) -; RV32I-FPELIM-NEXT: lw a1, 0(a0) -; RV32I-FPELIM-NEXT: addi a0, a0, 7 -; RV32I-FPELIM-NEXT: andi a0, a0, -4 -; RV32I-FPELIM-NEXT: addi a2, a0, 4 -; RV32I-FPELIM-NEXT: sw a2, 4(sp) -; RV32I-FPELIM-NEXT: lw a2, 0(a0) -; RV32I-FPELIM-NEXT: addi a0, a0, 7 -; RV32I-FPELIM-NEXT: andi a0, a0, -4 -; RV32I-FPELIM-NEXT: addi a3, a0, 4 -; RV32I-FPELIM-NEXT: sw a3, 4(sp) -; RV32I-FPELIM-NEXT: add a1, a1, s0 -; RV32I-FPELIM-NEXT: add a1, a1, a2 -; RV32I-FPELIM-NEXT: lw a0, 0(a0) -; RV32I-FPELIM-NEXT: add a0, a1, a0 -; RV32I-FPELIM-NEXT: lw s0, 8(sp) -; RV32I-FPELIM-NEXT: lw ra, 12(sp) -; RV32I-FPELIM-NEXT: addi sp, sp, 48 -; RV32I-FPELIM-NEXT: ret +; ILP32-ILP32F-FPELIM-LABEL: va4_va_copy: +; ILP32-ILP32F-FPELIM: # %bb.0: +; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -48 +; ILP32-ILP32F-FPELIM-NEXT: sw ra, 12(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw s0, 8(sp) +; ILP32-ILP32F-FPELIM-NEXT: mv s0, a1 +; ILP32-ILP32F-FPELIM-NEXT: sw a7, 44(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a6, 40(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a5, 36(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a4, 32(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a3, 28(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a2, 24(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a1, 20(sp) +; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 24 +; ILP32-ILP32F-FPELIM-NEXT: sw a0, 4(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a0, 0(sp) +; ILP32-ILP32F-FPELIM-NEXT: call notdead +; ILP32-ILP32F-FPELIM-NEXT: lw a0, 4(sp) +; ILP32-ILP32F-FPELIM-NEXT: addi a0, a0, 3 +; ILP32-ILP32F-FPELIM-NEXT: andi a0, a0, -4 +; ILP32-ILP32F-FPELIM-NEXT: addi a1, a0, 4 +; ILP32-ILP32F-FPELIM-NEXT: sw a1, 4(sp) +; ILP32-ILP32F-FPELIM-NEXT: lw a1, 0(a0) +; ILP32-ILP32F-FPELIM-NEXT: addi a0, a0, 7 +; ILP32-ILP32F-FPELIM-NEXT: andi a0, a0, -4 +; ILP32-ILP32F-FPELIM-NEXT: addi a2, a0, 4 +; ILP32-ILP32F-FPELIM-NEXT: sw a2, 4(sp) +; ILP32-ILP32F-FPELIM-NEXT: lw a2, 0(a0) +; ILP32-ILP32F-FPELIM-NEXT: addi a0, a0, 7 +; ILP32-ILP32F-FPELIM-NEXT: andi a0, a0, -4 +; ILP32-ILP32F-FPELIM-NEXT: addi a3, a0, 4 +; ILP32-ILP32F-FPELIM-NEXT: sw a3, 4(sp) +; ILP32-ILP32F-FPELIM-NEXT: add a1, a1, s0 +; ILP32-ILP32F-FPELIM-NEXT: add a1, a1, a2 +; ILP32-ILP32F-FPELIM-NEXT: lw a0, 0(a0) +; ILP32-ILP32F-FPELIM-NEXT: add a0, a1, a0 +; ILP32-ILP32F-FPELIM-NEXT: lw s0, 8(sp) +; ILP32-ILP32F-FPELIM-NEXT: lw ra, 12(sp) +; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48 +; ILP32-ILP32F-FPELIM-NEXT: ret ; -; RV32I-WITHFP-LABEL: va4_va_copy: -; RV32I-WITHFP: # %bb.0: -; RV32I-WITHFP-NEXT: addi sp, sp, -64 -; RV32I-WITHFP-NEXT: sw ra, 28(sp) -; RV32I-WITHFP-NEXT: sw s0, 24(sp) -; RV32I-WITHFP-NEXT: sw s1, 20(sp) -; RV32I-WITHFP-NEXT: addi s0, sp, 32 -; RV32I-WITHFP-NEXT: mv s1, a1 -; RV32I-WITHFP-NEXT: sw a7, 28(s0) -; RV32I-WITHFP-NEXT: sw a6, 24(s0) -; RV32I-WITHFP-NEXT: sw a5, 20(s0) -; RV32I-WITHFP-NEXT: sw a4, 16(s0) -; RV32I-WITHFP-NEXT: sw a3, 12(s0) -; RV32I-WITHFP-NEXT: sw a2, 8(s0) -; RV32I-WITHFP-NEXT: sw a1, 4(s0) -; RV32I-WITHFP-NEXT: addi a0, s0, 8 -; RV32I-WITHFP-NEXT: sw a0, -16(s0) -; RV32I-WITHFP-NEXT: sw a0, -20(s0) -; RV32I-WITHFP-NEXT: call notdead -; RV32I-WITHFP-NEXT: lw a0, -16(s0) -; RV32I-WITHFP-NEXT: addi a0, a0, 3 -; RV32I-WITHFP-NEXT: andi a0, a0, -4 -; RV32I-WITHFP-NEXT: addi a1, a0, 4 -; RV32I-WITHFP-NEXT: sw a1, -16(s0) -; RV32I-WITHFP-NEXT: lw a1, 0(a0) -; RV32I-WITHFP-NEXT: addi a0, a0, 7 -; RV32I-WITHFP-NEXT: andi a0, a0, -4 -; RV32I-WITHFP-NEXT: addi a2, a0, 4 -; RV32I-WITHFP-NEXT: sw a2, -16(s0) -; RV32I-WITHFP-NEXT: lw a2, 0(a0) -; RV32I-WITHFP-NEXT: addi a0, a0, 7 -; RV32I-WITHFP-NEXT: andi a0, a0, -4 -; RV32I-WITHFP-NEXT: addi a3, a0, 4 -; RV32I-WITHFP-NEXT: sw a3, -16(s0) -; RV32I-WITHFP-NEXT: add a1, a1, s1 -; RV32I-WITHFP-NEXT: add a1, a1, a2 -; RV32I-WITHFP-NEXT: lw a0, 0(a0) -; RV32I-WITHFP-NEXT: add a0, a1, a0 -; RV32I-WITHFP-NEXT: lw s1, 20(sp) -; RV32I-WITHFP-NEXT: lw s0, 24(sp) -; RV32I-WITHFP-NEXT: lw ra, 28(sp) -; RV32I-WITHFP-NEXT: addi sp, sp, 64 -; RV32I-WITHFP-NEXT: ret +; ILP32-ILP32F-WITHFP-LABEL: va4_va_copy: +; ILP32-ILP32F-WITHFP: # %bb.0: +; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -64 +; ILP32-ILP32F-WITHFP-NEXT: sw ra, 28(sp) +; ILP32-ILP32F-WITHFP-NEXT: sw s0, 24(sp) +; ILP32-ILP32F-WITHFP-NEXT: sw s1, 20(sp) +; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 32 +; ILP32-ILP32F-WITHFP-NEXT: mv s1, a1 +; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0) +; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 8 +; ILP32-ILP32F-WITHFP-NEXT: sw a0, -16(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a0, -20(s0) +; ILP32-ILP32F-WITHFP-NEXT: call notdead +; ILP32-ILP32F-WITHFP-NEXT: lw a0, -16(s0) +; ILP32-ILP32F-WITHFP-NEXT: addi a0, a0, 3 +; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -4 +; ILP32-ILP32F-WITHFP-NEXT: addi a1, a0, 4 +; ILP32-ILP32F-WITHFP-NEXT: sw a1, -16(s0) +; ILP32-ILP32F-WITHFP-NEXT: lw a1, 0(a0) +; ILP32-ILP32F-WITHFP-NEXT: addi a0, a0, 7 +; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -4 +; ILP32-ILP32F-WITHFP-NEXT: addi a2, a0, 4 +; ILP32-ILP32F-WITHFP-NEXT: sw a2, -16(s0) +; ILP32-ILP32F-WITHFP-NEXT: lw a2, 0(a0) +; ILP32-ILP32F-WITHFP-NEXT: addi a0, a0, 7 +; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -4 +; ILP32-ILP32F-WITHFP-NEXT: addi a3, a0, 4 +; ILP32-ILP32F-WITHFP-NEXT: sw a3, -16(s0) +; ILP32-ILP32F-WITHFP-NEXT: add a1, a1, s1 +; ILP32-ILP32F-WITHFP-NEXT: add a1, a1, a2 +; ILP32-ILP32F-WITHFP-NEXT: lw a0, 0(a0) +; ILP32-ILP32F-WITHFP-NEXT: add a0, a1, a0 +; ILP32-ILP32F-WITHFP-NEXT: lw s1, 20(sp) +; ILP32-ILP32F-WITHFP-NEXT: lw s0, 24(sp) +; ILP32-ILP32F-WITHFP-NEXT: lw ra, 28(sp) +; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 64 +; ILP32-ILP32F-WITHFP-NEXT: ret +; +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va4_va_copy: +; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw ra, 12(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw s0, 8(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv s0, a1 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 44(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 36(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 32(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 28(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 24(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 20(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 24 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 4(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 0(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call notdead +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a0, 4(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a0, 3 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -4 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, a0, 4 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 4(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a1, 0(a0) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a0, 7 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -4 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a2, a0, 4 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 4(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a2, 0(a0) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a0, 7 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -4 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a3, a0, 4 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 4(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a1, a1, s0 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a1, a1, a2 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a0, 0(a0) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a0, a1, a0 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw s0, 8(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 12(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 48 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret +; +; LP64-LP64F-LP64D-FPELIM-LABEL: va4_va_copy: +; LP64-LP64F-LP64D-FPELIM: # %bb.0: +; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -96 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd ra, 24(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd s0, 16(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: mv s0, a1 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a7, 88(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a6, 80(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 72(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 64(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 56(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 48(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 40(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, sp, 40 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 8 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 0(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: call notdead +; LP64-LP64F-LP64D-FPELIM-NEXT: ld a0, 8(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 3 +; LP64-LP64F-LP64D-FPELIM-NEXT: andi a0, a0, -4 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, a0, 8 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 8(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: ld a1, 0(a0) +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 11 +; LP64-LP64F-LP64D-FPELIM-NEXT: andi a0, a0, -4 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a2, a0, 8 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 8(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: ld a2, 0(a0) +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 11 +; LP64-LP64F-LP64D-FPELIM-NEXT: andi a0, a0, -4 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a3, a0, 8 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 8(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: add a1, a1, s0 +; LP64-LP64F-LP64D-FPELIM-NEXT: add a1, a1, a2 +; LP64-LP64F-LP64D-FPELIM-NEXT: ld a0, 0(a0) +; LP64-LP64F-LP64D-FPELIM-NEXT: add a0, a1, a0 +; LP64-LP64F-LP64D-FPELIM-NEXT: ld s0, 16(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: ld ra, 24(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 96 +; LP64-LP64F-LP64D-FPELIM-NEXT: ret +; +; LP64-LP64F-LP64D-WITHFP-LABEL: va4_va_copy: +; LP64-LP64F-LP64D-WITHFP: # %bb.0: +; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -112 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 40(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 32(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd s1, 24(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 48 +; LP64-LP64F-LP64D-WITHFP-NEXT: mv s1, a1 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 8 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 8 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -32(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -40(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: call notdead +; LP64-LP64F-LP64D-WITHFP-NEXT: ld a0, -32(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 3 +; LP64-LP64F-LP64D-WITHFP-NEXT: andi a0, a0, -4 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, a0, 8 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, -32(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: ld a1, 0(a0) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 11 +; LP64-LP64F-LP64D-WITHFP-NEXT: andi a0, a0, -4 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a2, a0, 8 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, -32(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: ld a2, 0(a0) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 11 +; LP64-LP64F-LP64D-WITHFP-NEXT: andi a0, a0, -4 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a3, a0, 8 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, -32(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: add a1, a1, s1 +; LP64-LP64F-LP64D-WITHFP-NEXT: add a1, a1, a2 +; LP64-LP64F-LP64D-WITHFP-NEXT: ld a0, 0(a0) +; LP64-LP64F-LP64D-WITHFP-NEXT: add a0, a1, a0 +; LP64-LP64F-LP64D-WITHFP-NEXT: ld s1, 24(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 32(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 40(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 112 +; LP64-LP64F-LP64D-WITHFP-NEXT: ret %vargs = alloca i8*, align 4 %wargs = alloca i8*, align 4 %1 = bitcast i8** %vargs to i8* @@ -636,133 +1382,243 @@ define i32 @va4_va_copy(i32 %argno, ...) nounwind { ; Check 2x*xlen values are aligned appropriately when passed on the stack in a vararg call -define i32 @va5_aligned_stack_callee(i32 %a, ...) nounwind { -; RV32I-FPELIM-LABEL: va5_aligned_stack_callee: -; RV32I-FPELIM: # %bb.0: -; RV32I-FPELIM-NEXT: addi sp, sp, -32 -; RV32I-FPELIM-NEXT: sw a7, 28(sp) -; RV32I-FPELIM-NEXT: sw a6, 24(sp) -; RV32I-FPELIM-NEXT: sw a5, 20(sp) -; RV32I-FPELIM-NEXT: sw a4, 16(sp) -; RV32I-FPELIM-NEXT: sw a3, 12(sp) -; RV32I-FPELIM-NEXT: sw a2, 8(sp) -; RV32I-FPELIM-NEXT: sw a1, 4(sp) -; RV32I-FPELIM-NEXT: addi a0, zero, 1 -; RV32I-FPELIM-NEXT: addi sp, sp, 32 -; RV32I-FPELIM-NEXT: ret -; -; RV32I-WITHFP-LABEL: va5_aligned_stack_callee: -; RV32I-WITHFP: # %bb.0: -; RV32I-WITHFP-NEXT: addi sp, sp, -48 -; RV32I-WITHFP-NEXT: sw ra, 12(sp) -; RV32I-WITHFP-NEXT: sw s0, 8(sp) -; RV32I-WITHFP-NEXT: addi s0, sp, 16 -; RV32I-WITHFP-NEXT: sw a7, 28(s0) -; RV32I-WITHFP-NEXT: sw a6, 24(s0) -; RV32I-WITHFP-NEXT: sw a5, 20(s0) -; RV32I-WITHFP-NEXT: sw a4, 16(s0) -; RV32I-WITHFP-NEXT: sw a3, 12(s0) -; RV32I-WITHFP-NEXT: sw a2, 8(s0) -; RV32I-WITHFP-NEXT: sw a1, 4(s0) -; RV32I-WITHFP-NEXT: addi a0, zero, 1 -; RV32I-WITHFP-NEXT: lw s0, 8(sp) -; RV32I-WITHFP-NEXT: lw ra, 12(sp) -; RV32I-WITHFP-NEXT: addi sp, sp, 48 -; RV32I-WITHFP-NEXT: ret - ret i32 1 -} +declare i32 @va5_aligned_stack_callee(i32, ...) define void @va5_aligned_stack_caller() nounwind { ; The double should be 8-byte aligned on the stack, but the two-element array ; should only be 4-byte aligned -; RV32I-FPELIM-LABEL: va5_aligned_stack_caller: -; RV32I-FPELIM: # %bb.0: -; RV32I-FPELIM-NEXT: addi sp, sp, -64 -; RV32I-FPELIM-NEXT: sw ra, 60(sp) -; RV32I-FPELIM-NEXT: addi a0, zero, 17 -; RV32I-FPELIM-NEXT: sw a0, 24(sp) -; RV32I-FPELIM-NEXT: addi a0, zero, 16 -; RV32I-FPELIM-NEXT: sw a0, 20(sp) -; RV32I-FPELIM-NEXT: addi a0, zero, 15 -; RV32I-FPELIM-NEXT: sw a0, 16(sp) -; RV32I-FPELIM-NEXT: lui a0, 262236 -; RV32I-FPELIM-NEXT: addi a0, a0, 655 -; RV32I-FPELIM-NEXT: sw a0, 12(sp) -; RV32I-FPELIM-NEXT: lui a0, 377487 -; RV32I-FPELIM-NEXT: addi a0, a0, 1475 -; RV32I-FPELIM-NEXT: sw a0, 8(sp) -; RV32I-FPELIM-NEXT: addi a0, zero, 14 -; RV32I-FPELIM-NEXT: sw a0, 0(sp) -; RV32I-FPELIM-NEXT: lui a0, 262153 -; RV32I-FPELIM-NEXT: addi a0, a0, 491 -; RV32I-FPELIM-NEXT: sw a0, 44(sp) -; RV32I-FPELIM-NEXT: lui a0, 545260 -; RV32I-FPELIM-NEXT: addi a0, a0, -1967 -; RV32I-FPELIM-NEXT: sw a0, 40(sp) -; RV32I-FPELIM-NEXT: lui a0, 964690 -; RV32I-FPELIM-NEXT: addi a0, a0, -328 -; RV32I-FPELIM-NEXT: sw a0, 36(sp) -; RV32I-FPELIM-NEXT: lui a0, 335544 -; RV32I-FPELIM-NEXT: addi a0, a0, 1311 -; RV32I-FPELIM-NEXT: sw a0, 32(sp) -; RV32I-FPELIM-NEXT: lui a0, 688509 -; RV32I-FPELIM-NEXT: addi a6, a0, -2048 -; RV32I-FPELIM-NEXT: addi a2, sp, 32 -; RV32I-FPELIM-NEXT: addi a0, zero, 1 -; RV32I-FPELIM-NEXT: addi a1, zero, 11 -; RV32I-FPELIM-NEXT: addi a3, zero, 12 -; RV32I-FPELIM-NEXT: addi a4, zero, 13 -; RV32I-FPELIM-NEXT: addi a7, zero, 4 -; RV32I-FPELIM-NEXT: call va5_aligned_stack_callee -; RV32I-FPELIM-NEXT: lw ra, 60(sp) -; RV32I-FPELIM-NEXT: addi sp, sp, 64 -; RV32I-FPELIM-NEXT: ret +; ILP32-ILP32F-FPELIM-LABEL: va5_aligned_stack_caller: +; ILP32-ILP32F-FPELIM: # %bb.0: +; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -64 +; ILP32-ILP32F-FPELIM-NEXT: sw ra, 60(sp) +; ILP32-ILP32F-FPELIM-NEXT: addi a0, zero, 17 +; ILP32-ILP32F-FPELIM-NEXT: sw a0, 24(sp) +; ILP32-ILP32F-FPELIM-NEXT: addi a0, zero, 16 +; ILP32-ILP32F-FPELIM-NEXT: sw a0, 20(sp) +; ILP32-ILP32F-FPELIM-NEXT: addi a0, zero, 15 +; ILP32-ILP32F-FPELIM-NEXT: sw a0, 16(sp) +; ILP32-ILP32F-FPELIM-NEXT: lui a0, 262236 +; ILP32-ILP32F-FPELIM-NEXT: addi a0, a0, 655 +; ILP32-ILP32F-FPELIM-NEXT: sw a0, 12(sp) +; ILP32-ILP32F-FPELIM-NEXT: lui a0, 377487 +; ILP32-ILP32F-FPELIM-NEXT: addi a0, a0, 1475 +; ILP32-ILP32F-FPELIM-NEXT: sw a0, 8(sp) +; ILP32-ILP32F-FPELIM-NEXT: addi a0, zero, 14 +; ILP32-ILP32F-FPELIM-NEXT: sw a0, 0(sp) +; ILP32-ILP32F-FPELIM-NEXT: lui a0, 262153 +; ILP32-ILP32F-FPELIM-NEXT: addi a0, a0, 491 +; ILP32-ILP32F-FPELIM-NEXT: sw a0, 44(sp) +; ILP32-ILP32F-FPELIM-NEXT: lui a0, 545260 +; ILP32-ILP32F-FPELIM-NEXT: addi a0, a0, -1967 +; ILP32-ILP32F-FPELIM-NEXT: sw a0, 40(sp) +; ILP32-ILP32F-FPELIM-NEXT: lui a0, 964690 +; ILP32-ILP32F-FPELIM-NEXT: addi a0, a0, -328 +; ILP32-ILP32F-FPELIM-NEXT: sw a0, 36(sp) +; ILP32-ILP32F-FPELIM-NEXT: lui a0, 335544 +; ILP32-ILP32F-FPELIM-NEXT: addi a0, a0, 1311 +; ILP32-ILP32F-FPELIM-NEXT: sw a0, 32(sp) +; ILP32-ILP32F-FPELIM-NEXT: lui a0, 688509 +; ILP32-ILP32F-FPELIM-NEXT: addi a6, a0, -2048 +; ILP32-ILP32F-FPELIM-NEXT: addi a2, sp, 32 +; ILP32-ILP32F-FPELIM-NEXT: addi a0, zero, 1 +; ILP32-ILP32F-FPELIM-NEXT: addi a1, zero, 11 +; ILP32-ILP32F-FPELIM-NEXT: addi a3, zero, 12 +; ILP32-ILP32F-FPELIM-NEXT: addi a4, zero, 13 +; ILP32-ILP32F-FPELIM-NEXT: addi a7, zero, 4 +; ILP32-ILP32F-FPELIM-NEXT: call va5_aligned_stack_callee +; ILP32-ILP32F-FPELIM-NEXT: lw ra, 60(sp) +; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 64 +; ILP32-ILP32F-FPELIM-NEXT: ret ; -; RV32I-WITHFP-LABEL: va5_aligned_stack_caller: -; RV32I-WITHFP: # %bb.0: -; RV32I-WITHFP-NEXT: addi sp, sp, -64 -; RV32I-WITHFP-NEXT: sw ra, 60(sp) -; RV32I-WITHFP-NEXT: sw s0, 56(sp) -; RV32I-WITHFP-NEXT: addi s0, sp, 64 -; RV32I-WITHFP-NEXT: addi a0, zero, 17 -; RV32I-WITHFP-NEXT: sw a0, 24(sp) -; RV32I-WITHFP-NEXT: addi a0, zero, 16 -; RV32I-WITHFP-NEXT: sw a0, 20(sp) -; RV32I-WITHFP-NEXT: addi a0, zero, 15 -; RV32I-WITHFP-NEXT: sw a0, 16(sp) -; RV32I-WITHFP-NEXT: lui a0, 262236 -; RV32I-WITHFP-NEXT: addi a0, a0, 655 -; RV32I-WITHFP-NEXT: sw a0, 12(sp) -; RV32I-WITHFP-NEXT: lui a0, 377487 -; RV32I-WITHFP-NEXT: addi a0, a0, 1475 -; RV32I-WITHFP-NEXT: sw a0, 8(sp) -; RV32I-WITHFP-NEXT: addi a0, zero, 14 -; RV32I-WITHFP-NEXT: sw a0, 0(sp) -; RV32I-WITHFP-NEXT: lui a0, 262153 -; RV32I-WITHFP-NEXT: addi a0, a0, 491 -; RV32I-WITHFP-NEXT: sw a0, -20(s0) -; RV32I-WITHFP-NEXT: lui a0, 545260 -; RV32I-WITHFP-NEXT: addi a0, a0, -1967 -; RV32I-WITHFP-NEXT: sw a0, -24(s0) -; RV32I-WITHFP-NEXT: lui a0, 964690 -; RV32I-WITHFP-NEXT: addi a0, a0, -328 -; RV32I-WITHFP-NEXT: sw a0, -28(s0) -; RV32I-WITHFP-NEXT: lui a0, 335544 -; RV32I-WITHFP-NEXT: addi a0, a0, 1311 -; RV32I-WITHFP-NEXT: sw a0, -32(s0) -; RV32I-WITHFP-NEXT: lui a0, 688509 -; RV32I-WITHFP-NEXT: addi a6, a0, -2048 -; RV32I-WITHFP-NEXT: addi a2, s0, -32 -; RV32I-WITHFP-NEXT: addi a0, zero, 1 -; RV32I-WITHFP-NEXT: addi a1, zero, 11 -; RV32I-WITHFP-NEXT: addi a3, zero, 12 -; RV32I-WITHFP-NEXT: addi a4, zero, 13 -; RV32I-WITHFP-NEXT: addi a7, zero, 4 -; RV32I-WITHFP-NEXT: call va5_aligned_stack_callee -; RV32I-WITHFP-NEXT: lw s0, 56(sp) -; RV32I-WITHFP-NEXT: lw ra, 60(sp) -; RV32I-WITHFP-NEXT: addi sp, sp, 64 -; RV32I-WITHFP-NEXT: ret +; ILP32-ILP32F-WITHFP-LABEL: va5_aligned_stack_caller: +; ILP32-ILP32F-WITHFP: # %bb.0: +; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -64 +; ILP32-ILP32F-WITHFP-NEXT: sw ra, 60(sp) +; ILP32-ILP32F-WITHFP-NEXT: sw s0, 56(sp) +; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 64 +; ILP32-ILP32F-WITHFP-NEXT: addi a0, zero, 17 +; ILP32-ILP32F-WITHFP-NEXT: sw a0, 24(sp) +; ILP32-ILP32F-WITHFP-NEXT: addi a0, zero, 16 +; ILP32-ILP32F-WITHFP-NEXT: sw a0, 20(sp) +; ILP32-ILP32F-WITHFP-NEXT: addi a0, zero, 15 +; ILP32-ILP32F-WITHFP-NEXT: sw a0, 16(sp) +; ILP32-ILP32F-WITHFP-NEXT: lui a0, 262236 +; ILP32-ILP32F-WITHFP-NEXT: addi a0, a0, 655 +; ILP32-ILP32F-WITHFP-NEXT: sw a0, 12(sp) +; ILP32-ILP32F-WITHFP-NEXT: lui a0, 377487 +; ILP32-ILP32F-WITHFP-NEXT: addi a0, a0, 1475 +; ILP32-ILP32F-WITHFP-NEXT: sw a0, 8(sp) +; ILP32-ILP32F-WITHFP-NEXT: addi a0, zero, 14 +; ILP32-ILP32F-WITHFP-NEXT: sw a0, 0(sp) +; ILP32-ILP32F-WITHFP-NEXT: lui a0, 262153 +; ILP32-ILP32F-WITHFP-NEXT: addi a0, a0, 491 +; ILP32-ILP32F-WITHFP-NEXT: sw a0, -20(s0) +; ILP32-ILP32F-WITHFP-NEXT: lui a0, 545260 +; ILP32-ILP32F-WITHFP-NEXT: addi a0, a0, -1967 +; ILP32-ILP32F-WITHFP-NEXT: sw a0, -24(s0) +; ILP32-ILP32F-WITHFP-NEXT: lui a0, 964690 +; ILP32-ILP32F-WITHFP-NEXT: addi a0, a0, -328 +; ILP32-ILP32F-WITHFP-NEXT: sw a0, -28(s0) +; ILP32-ILP32F-WITHFP-NEXT: lui a0, 335544 +; ILP32-ILP32F-WITHFP-NEXT: addi a0, a0, 1311 +; ILP32-ILP32F-WITHFP-NEXT: sw a0, -32(s0) +; ILP32-ILP32F-WITHFP-NEXT: lui a0, 688509 +; ILP32-ILP32F-WITHFP-NEXT: addi a6, a0, -2048 +; ILP32-ILP32F-WITHFP-NEXT: addi a2, s0, -32 +; ILP32-ILP32F-WITHFP-NEXT: addi a0, zero, 1 +; ILP32-ILP32F-WITHFP-NEXT: addi a1, zero, 11 +; ILP32-ILP32F-WITHFP-NEXT: addi a3, zero, 12 +; ILP32-ILP32F-WITHFP-NEXT: addi a4, zero, 13 +; ILP32-ILP32F-WITHFP-NEXT: addi a7, zero, 4 +; ILP32-ILP32F-WITHFP-NEXT: call va5_aligned_stack_callee +; ILP32-ILP32F-WITHFP-NEXT: lw s0, 56(sp) +; ILP32-ILP32F-WITHFP-NEXT: lw ra, 60(sp) +; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 64 +; ILP32-ILP32F-WITHFP-NEXT: ret +; +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va5_aligned_stack_caller: +; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -64 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw ra, 60(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a0, 262236 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a0, 655 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 12(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a0, 377487 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a0, 1475 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 8(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, zero, 17 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 24(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, zero, 16 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 20(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, zero, 15 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 16(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, zero, 14 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 0(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a0, 262153 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a0, 491 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 44(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a0, 545260 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a0, -1967 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 40(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a0, 964690 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a0, -328 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 36(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a0, 335544 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a0, 1311 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 32(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a0, 688509 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a6, a0, -2048 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a2, sp, 32 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, zero, 1 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, zero, 11 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a3, zero, 12 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a4, zero, 13 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a7, zero, 4 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call va5_aligned_stack_callee +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 60(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 64 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret +; +; LP64-LP64F-LP64D-FPELIM-LABEL: va5_aligned_stack_caller: +; LP64-LP64F-LP64D-FPELIM: # %bb.0: +; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -48 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd ra, 40(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 17 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 24(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 16 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 16(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 15 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: lui a0, 2049 +; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a0, a0, -1147 +; LP64-LP64F-LP64D-FPELIM-NEXT: slli a0, a0, 13 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 983 +; LP64-LP64F-LP64D-FPELIM-NEXT: slli a0, a0, 14 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 655 +; LP64-LP64F-LP64D-FPELIM-NEXT: slli a0, a0, 12 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 1475 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 0(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: lui a0, 1048248 +; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a0, a0, 1311 +; LP64-LP64F-LP64D-FPELIM-NEXT: slli a0, a0, 12 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, -1147 +; LP64-LP64F-LP64D-FPELIM-NEXT: slli a0, a0, 13 +; LP64-LP64F-LP64D-FPELIM-NEXT: lui a1, 512 +; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a1, a1, 73 +; LP64-LP64F-LP64D-FPELIM-NEXT: slli a1, a1, 15 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, a1, -1311 +; LP64-LP64F-LP64D-FPELIM-NEXT: slli a1, a1, 12 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, a1, 1147 +; LP64-LP64F-LP64D-FPELIM-NEXT: slli a1, a1, 14 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 983 +; LP64-LP64F-LP64D-FPELIM-NEXT: slli a0, a0, 15 +; LP64-LP64F-LP64D-FPELIM-NEXT: lui a2, 1192 +; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a2, a2, 381 +; LP64-LP64F-LP64D-FPELIM-NEXT: slli a2, a2, 12 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a6, a2, -2048 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a2, a0, 1311 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a3, a1, -1967 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 1 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, zero, 11 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a4, zero, 12 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a5, zero, 13 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a7, zero, 14 +; LP64-LP64F-LP64D-FPELIM-NEXT: call va5_aligned_stack_callee +; LP64-LP64F-LP64D-FPELIM-NEXT: ld ra, 40(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 48 +; LP64-LP64F-LP64D-FPELIM-NEXT: ret +; +; LP64-LP64F-LP64D-WITHFP-LABEL: va5_aligned_stack_caller: +; LP64-LP64F-LP64D-WITHFP: # %bb.0: +; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -48 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 40(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 32(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 48 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 17 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, 24(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 16 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, 16(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 15 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, 8(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: lui a0, 2049 +; LP64-LP64F-LP64D-WITHFP-NEXT: addiw a0, a0, -1147 +; LP64-LP64F-LP64D-WITHFP-NEXT: slli a0, a0, 13 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 983 +; LP64-LP64F-LP64D-WITHFP-NEXT: slli a0, a0, 14 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 655 +; LP64-LP64F-LP64D-WITHFP-NEXT: slli a0, a0, 12 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 1475 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, 0(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: lui a0, 1048248 +; LP64-LP64F-LP64D-WITHFP-NEXT: addiw a0, a0, 1311 +; LP64-LP64F-LP64D-WITHFP-NEXT: slli a0, a0, 12 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, -1147 +; LP64-LP64F-LP64D-WITHFP-NEXT: slli a0, a0, 13 +; LP64-LP64F-LP64D-WITHFP-NEXT: lui a1, 512 +; LP64-LP64F-LP64D-WITHFP-NEXT: addiw a1, a1, 73 +; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a1, 15 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, a1, -1311 +; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a1, 12 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, a1, 1147 +; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a1, 14 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 983 +; LP64-LP64F-LP64D-WITHFP-NEXT: slli a0, a0, 15 +; LP64-LP64F-LP64D-WITHFP-NEXT: lui a2, 1192 +; LP64-LP64F-LP64D-WITHFP-NEXT: addiw a2, a2, 381 +; LP64-LP64F-LP64D-WITHFP-NEXT: slli a2, a2, 12 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a6, a2, -2048 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a2, a0, 1311 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a3, a1, -1967 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 1 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, zero, 11 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a4, zero, 12 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a5, zero, 13 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a7, zero, 14 +; LP64-LP64F-LP64D-WITHFP-NEXT: call va5_aligned_stack_callee +; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 32(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 40(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 48 +; LP64-LP64F-LP64D-WITHFP-NEXT: ret %1 = call i32 (i32, ...) @va5_aligned_stack_callee(i32 1, i32 11, fp128 0xLEB851EB851EB851F400091EB851EB851, i32 12, i32 13, i64 20000000000, i32 14, double 2.720000e+00, i32 15, [2 x i32] [i32 16, i32 17]) @@ -774,42 +1630,97 @@ define void @va5_aligned_stack_caller() nounwind { ; still set up correctly. define i32 @va6_no_fixed_args(...) nounwind { -; RV32I-FPELIM-LABEL: va6_no_fixed_args: -; RV32I-FPELIM: # %bb.0: -; RV32I-FPELIM-NEXT: addi sp, sp, -48 -; RV32I-FPELIM-NEXT: sw a7, 44(sp) -; RV32I-FPELIM-NEXT: sw a6, 40(sp) -; RV32I-FPELIM-NEXT: sw a5, 36(sp) -; RV32I-FPELIM-NEXT: sw a4, 32(sp) -; RV32I-FPELIM-NEXT: sw a3, 28(sp) -; RV32I-FPELIM-NEXT: sw a2, 24(sp) -; RV32I-FPELIM-NEXT: sw a1, 20(sp) -; RV32I-FPELIM-NEXT: addi a1, sp, 20 -; RV32I-FPELIM-NEXT: sw a1, 12(sp) -; RV32I-FPELIM-NEXT: sw a0, 16(sp) -; RV32I-FPELIM-NEXT: addi sp, sp, 48 -; RV32I-FPELIM-NEXT: ret +; ILP32-ILP32F-FPELIM-LABEL: va6_no_fixed_args: +; ILP32-ILP32F-FPELIM: # %bb.0: +; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -48 +; ILP32-ILP32F-FPELIM-NEXT: sw a7, 44(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a6, 40(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a5, 36(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a4, 32(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a3, 28(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a2, 24(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a1, 20(sp) +; ILP32-ILP32F-FPELIM-NEXT: addi a1, sp, 20 +; ILP32-ILP32F-FPELIM-NEXT: sw a1, 12(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a0, 16(sp) +; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48 +; ILP32-ILP32F-FPELIM-NEXT: ret ; -; RV32I-WITHFP-LABEL: va6_no_fixed_args: -; RV32I-WITHFP: # %bb.0: -; RV32I-WITHFP-NEXT: addi sp, sp, -48 -; RV32I-WITHFP-NEXT: sw ra, 12(sp) -; RV32I-WITHFP-NEXT: sw s0, 8(sp) -; RV32I-WITHFP-NEXT: addi s0, sp, 16 -; RV32I-WITHFP-NEXT: sw a7, 28(s0) -; RV32I-WITHFP-NEXT: sw a6, 24(s0) -; RV32I-WITHFP-NEXT: sw a5, 20(s0) -; RV32I-WITHFP-NEXT: sw a4, 16(s0) -; RV32I-WITHFP-NEXT: sw a3, 12(s0) -; RV32I-WITHFP-NEXT: sw a2, 8(s0) -; RV32I-WITHFP-NEXT: sw a1, 4(s0) -; RV32I-WITHFP-NEXT: addi a1, s0, 4 -; RV32I-WITHFP-NEXT: sw a1, -12(s0) -; RV32I-WITHFP-NEXT: sw a0, 0(s0) -; RV32I-WITHFP-NEXT: lw s0, 8(sp) -; RV32I-WITHFP-NEXT: lw ra, 12(sp) -; RV32I-WITHFP-NEXT: addi sp, sp, 48 -; RV32I-WITHFP-NEXT: ret +; ILP32-ILP32F-WITHFP-LABEL: va6_no_fixed_args: +; ILP32-ILP32F-WITHFP: # %bb.0: +; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48 +; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp) +; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) +; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16 +; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0) +; ILP32-ILP32F-WITHFP-NEXT: addi a1, s0, 4 +; ILP32-ILP32F-WITHFP-NEXT: sw a1, -12(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a0, 0(s0) +; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) +; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) +; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48 +; ILP32-ILP32F-WITHFP-NEXT: ret +; +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va6_no_fixed_args: +; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 44(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 36(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 32(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 28(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 24(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 20(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, sp, 20 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 12(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 16(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 48 +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret +; +; LP64-LP64F-LP64D-FPELIM-LABEL: va6_no_fixed_args: +; LP64-LP64F-LP64D-FPELIM: # %bb.0: +; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -80 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a7, 72(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a6, 64(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 56(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 48(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 40(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 32(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 24(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, sp, 16 +; LP64-LP64F-LP64D-FPELIM-NEXT: ori a1, a1, 8 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 8(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 16(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 80 +; LP64-LP64F-LP64D-FPELIM-NEXT: ret +; +; LP64-LP64F-LP64D-WITHFP-LABEL: va6_no_fixed_args: +; LP64-LP64F-LP64D-WITHFP: # %bb.0: +; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -96 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: mv a1, s0 +; LP64-LP64F-LP64D-WITHFP-NEXT: ori a1, a1, 8 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, -24(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, 0(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 96 +; LP64-LP64F-LP64D-WITHFP-NEXT: ret %va = alloca i8*, align 4 %1 = bitcast i8** %va to i8* call void @llvm.va_start(i8* %1)