From b545c253d675e1609af6420aece3d70c37c5ae2a Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Tue, 20 Aug 2013 09:47:12 +0000 Subject: [PATCH] [mips][msa] Added fexdo, fexup[lr] builtins llvm-svn: 188784 --- clang/include/clang/Basic/BuiltinsMips.def | 9 +++++++++ clang/test/CodeGen/builtins-mips-msa.c | 9 +++++++++ 2 files changed, 18 insertions(+) diff --git a/clang/include/clang/Basic/BuiltinsMips.def b/clang/include/clang/Basic/BuiltinsMips.def index dc3373b23e78..6d0db0e82c2d 100644 --- a/clang/include/clang/Basic/BuiltinsMips.def +++ b/clang/include/clang/Basic/BuiltinsMips.def @@ -418,9 +418,18 @@ BUILTIN(__builtin_msa_fcne_d, "V2LLiV2dV2d", "nc") BUILTIN(__builtin_msa_fdiv_w, "V4fV4fV4f", "nc") BUILTIN(__builtin_msa_fdiv_d, "V2dV2dV2d", "nc") +BUILTIN(__builtin_msa_fexdo_h, "V8hV4fV4f", "nc") +BUILTIN(__builtin_msa_fexdo_w, "V4fV2dV2d", "nc") + BUILTIN(__builtin_msa_fexp2_w, "V4fV4fV4i", "nc") BUILTIN(__builtin_msa_fexp2_d, "V2dV2dV2LLi", "nc") +BUILTIN(__builtin_msa_fexupl_w, "V4fV8h", "nc") +BUILTIN(__builtin_msa_fexupl_d, "V2dV4f", "nc") + +BUILTIN(__builtin_msa_fexupr_w, "V4fV8h", "nc") +BUILTIN(__builtin_msa_fexupr_d, "V2dV4f", "nc") + BUILTIN(__builtin_msa_ffint_s_w, "V4fV4Si", "nc") BUILTIN(__builtin_msa_ffint_s_d, "V2dV2SLLi", "nc") diff --git a/clang/test/CodeGen/builtins-mips-msa.c b/clang/test/CodeGen/builtins-mips-msa.c index 54ca53ddf525..d9349d60cd0c 100644 --- a/clang/test/CodeGen/builtins-mips-msa.c +++ b/clang/test/CodeGen/builtins-mips-msa.c @@ -303,9 +303,18 @@ void test(void) { v4f32_r = __builtin_msa_fdiv_w(v4f32_a, v4f32_b); // CHECK: call <4 x float> @llvm.mips.fdiv.w( v2f64_r = __builtin_msa_fdiv_d(v2f64_a, v2f64_b); // CHECK: call <2 x double> @llvm.mips.fdiv.d( + v8f16_r = __builtin_msa_fexdo_h(v4f32_a, v4f32_b); // CHECK: call <8 x half> @llvm.mips.fexdo.h( + v4f32_r = __builtin_msa_fexdo_w(v2f64_a, v2f64_b); // CHECK: call <4 x float> @llvm.mips.fexdo.w( + v4f32_r = __builtin_msa_fexp2_w(v4f32_a, v4i32_b); // CHECK: call <4 x float> @llvm.mips.fexp2.w( v2f64_r = __builtin_msa_fexp2_d(v2f64_a, v2i64_b); // CHECK: call <2 x double> @llvm.mips.fexp2.d( + v4f32_r = __builtin_msa_fexupl_w(v8f16_a); // CHECK: call <4 x float> @llvm.mips.fexupl.w( + v2f64_r = __builtin_msa_fexupl_d(v4f32_a); // CHECK: call <2 x double> @llvm.mips.fexupl.d( + + v4f32_r = __builtin_msa_fexupr_w(v8f16_a); // CHECK: call <4 x float> @llvm.mips.fexupr.w( + v2f64_r = __builtin_msa_fexupr_d(v4f32_a); // CHECK: call <2 x double> @llvm.mips.fexupr.d( + v4f32_r = __builtin_msa_ffint_s_w(v4i32_a); // CHECK: call <4 x float> @llvm.mips.ffint.s.w( v2f64_r = __builtin_msa_ffint_s_d(v2i64_a); // CHECK: call <2 x double> @llvm.mips.ffint.s.d(