forked from OSchip/llvm-project
parent
9f4530b95d
commit
b5459e6e22
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@ -626,6 +626,13 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
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// Altivec instructions set fields to all zeros or all ones.
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setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
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if (!isPPC64) {
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// These libcalls are not available in 32-bit.
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setLibcallName(RTLIB::SHL_I128, nullptr);
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setLibcallName(RTLIB::SRL_I128, nullptr);
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setLibcallName(RTLIB::SRA_I128, nullptr);
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}
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if (isPPC64) {
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setStackPointerRegisterToSaveRestore(PPC::X1);
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setExceptionPointerRegister(PPC::X3);
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@ -0,0 +1,39 @@
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; RUN: llc -O=2 < %s -mtriple=powerpc-netbsd | FileCheck %s
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; CHECK-NOT: bl __lshrti3
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; ModuleID = 'lshrti3-ppc32.c'
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target datalayout = "E-m:e-p:32:32-i64:64-n32"
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target triple = "powerpc--netbsd"
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; Function Attrs: nounwind uwtable
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define i32 @fn1() #0 {
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entry:
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%.promoted = load i72* inttoptr (i32 1 to i72*), align 4
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br label %while.cond
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while.cond: ; preds = %while.cond, %entry
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%bf.set3 = phi i72 [ %bf.set, %while.cond ], [ %.promoted, %entry ]
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%bf.lshr = lshr i72 %bf.set3, 40
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%bf.lshr.tr = trunc i72 %bf.lshr to i32
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%bf.cast = and i32 %bf.lshr.tr, 65535
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%dec = add nsw i32 %bf.lshr.tr, 65535
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%0 = zext i32 %dec to i72
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%bf.value = shl nuw i72 %0, 40
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%bf.shl = and i72 %bf.value, 72056494526300160
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%bf.clear2 = and i72 %bf.set3, -72056494526300161
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%bf.set = or i72 %bf.shl, %bf.clear2
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%tobool = icmp eq i32 %bf.cast, 0
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br i1 %tobool, label %while.end, label %while.cond
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while.end: ; preds = %while.cond
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%bf.set.lcssa = phi i72 [ %bf.set, %while.cond ]
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store i72 %bf.set.lcssa, i72* inttoptr (i32 1 to i72*), align 4
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ret i32 undef
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}
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attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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!llvm.ident = !{!0}
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!0 = metadata !{metadata !"clang version 3.5.0 (213754)"}
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