forked from OSchip/llvm-project
Cleanup the trunc-store legalization code and add asserts.
llvm-svn: 141659
This commit is contained in:
Nadav Rotem
parent
c8a78ded33
commit
b521b6037b
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@ -1607,82 +1607,101 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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EVT WideScalarVT = Tmp3.getValueType().getScalarType();
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EVT WideScalarVT = Tmp3.getValueType().getScalarType();
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EVT NarrowScalarVT = StVT.getScalarType();
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EVT NarrowScalarVT = StVT.getScalarType();
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// The Store type is illegal, must scalarize the vector store.
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if (StVT.isVector()) {
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SmallVector<SDValue, 8> Stores;
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bool ScalarLegal = TLI.isTypeLegal(WideScalarVT);
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if (!TLI.isTypeLegal(StVT) && StVT.isVector() && ScalarLegal) {
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unsigned NumElem = StVT.getVectorNumElements();
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unsigned NumElem = StVT.getVectorNumElements();
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// The type of the data we want to save
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EVT RegVT = Tmp3.getValueType();
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EVT RegSclVT = RegVT.getScalarType();
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// The type of data as saved in memory.
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EVT MemSclVT = StVT.getScalarType();
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unsigned ScalarSize = StVT.getScalarType().getSizeInBits();
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bool RegScalarLegal = TLI.isTypeLegal(RegSclVT);
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EVT EltVT = EVT::getIntegerVT(*DAG.getContext(), ScalarSize);
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bool MemScalarLegal = TLI.isTypeLegal(MemSclVT);
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assert(TLI.isTypeLegal(EltVT) && "Scalar store type must be legal");
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// Round odd types to the next pow of two.
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// We need to expand this store. If both the reg-scalar and the
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if (!isPowerOf2_32(ScalarSize))
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// memory-scalar are of legal types, then scalarize the vector.
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ScalarSize = NextPowerOf2(ScalarSize);
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if (RegScalarLegal && MemScalarLegal) {
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// Types smaller than 8 bits are promoted to 8 bits.
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// Cast floats into integers
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ScalarSize = std::max<unsigned>(ScalarSize, 8);
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unsigned ScalarSize = MemSclVT.getSizeInBits();
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// Store stride
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EVT EltVT = EVT::getIntegerVT(*DAG.getContext(), ScalarSize);
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unsigned Stride = ScalarSize/8;
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assert(TLI.isTypeLegal(EltVT) && "Saved scalars must be legal");
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assert(isPowerOf2_32(Stride) && "Stride must be a power of two");
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for (unsigned Idx=0; Idx<NumElem; Idx++) {
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// Round odd types to the next pow of two.
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SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
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if (!isPowerOf2_32(ScalarSize))
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WideScalarVT, Tmp3, DAG.getIntPtrConstant(Idx));
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ScalarSize = NextPowerOf2(ScalarSize);
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Ex = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Ex);
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// Store Stride in bytes
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Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
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unsigned Stride = ScalarSize/8;
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DAG.getIntPtrConstant(Stride));
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// Extract each of the elements from the original vector
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SDValue Store = DAG.getStore(Tmp1, dl, Ex, Tmp2,
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// and save them into memory individually.
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ST->getPointerInfo().getWithOffset(Idx*Stride),
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SmallVector<SDValue, 8> Stores;
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isVolatile, isNonTemporal, Alignment);
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for (unsigned Idx = 0; Idx < NumElem; Idx++) {
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Stores.push_back(Store);
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SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
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}
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RegSclVT, Tmp3, DAG.getIntPtrConstant(Idx));
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Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
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&Stores[0], Stores.size());
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break;
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}
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// The Store type is illegal, must scalarize the vector store.
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Ex = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Ex);
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// However, the scalar type is illegal. Must bitcast the result
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Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
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// and store it in smaller parts.
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DAG.getIntPtrConstant(Stride));
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if (!TLI.isTypeLegal(StVT) && StVT.isVector()) {
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unsigned WideNumElem = StVT.getVectorNumElements();
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unsigned Stride = NarrowScalarVT.getSizeInBits()/8;
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unsigned SizeRatio =
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(WideScalarVT.getSizeInBits() / NarrowScalarVT.getSizeInBits());
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EVT CastValueVT = EVT::getVectorVT(*DAG.getContext(), NarrowScalarVT,
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SizeRatio*WideNumElem);
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// Cast the wide elem vector to wider vec with smaller elem type.
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// Example <2 x i64> -> <4 x i32>
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Tmp3 = DAG.getNode(ISD::BITCAST, dl, CastValueVT, Tmp3);
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for (unsigned Idx=0; Idx<WideNumElem*SizeRatio; Idx++) {
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// Extract elment i
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SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
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NarrowScalarVT, Tmp3, DAG.getIntPtrConstant(Idx));
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// bump pointer.
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Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
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DAG.getIntPtrConstant(Stride));
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// Store if, this element is:
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// - First element on big endian, or
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// - Last element on little endian
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if (( TLI.isBigEndian() && (Idx%SizeRatio == 0)) ||
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((!TLI.isBigEndian() && (Idx%SizeRatio == SizeRatio-1)))) {
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SDValue Store = DAG.getStore(Tmp1, dl, Ex, Tmp2,
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SDValue Store = DAG.getStore(Tmp1, dl, Ex, Tmp2,
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ST->getPointerInfo().getWithOffset(Idx*Stride),
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ST->getPointerInfo().getWithOffset(Idx*Stride),
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isVolatile, isNonTemporal, Alignment);
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isVolatile, isNonTemporal, Alignment);
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Stores.push_back(Store);
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Stores.push_back(Store);
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}
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}
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Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
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&Stores[0], Stores.size());
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break;
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}
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}
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Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
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&Stores[0], Stores.size());
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break;
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// The scalar register type is illegal.
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}
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// For example saving <2 x i64> -> <2 x i32> on a x86.
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// In here we bitcast the value into a vector of smaller parts and
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// save it using smaller scalars.
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if (!RegScalarLegal && MemScalarLegal) {
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// Store Stride in bytes
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unsigned Stride = MemSclVT.getSizeInBits()/8;
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unsigned SizeRatio =
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(RegSclVT.getSizeInBits() / MemSclVT.getSizeInBits());
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EVT CastValueVT = EVT::getVectorVT(*DAG.getContext(),
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MemSclVT,
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SizeRatio * NumElem);
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// Cast the wide elem vector to wider vec with smaller elem type.
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// Example <2 x i64> -> <4 x i32>
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Tmp3 = DAG.getNode(ISD::BITCAST, dl, CastValueVT, Tmp3);
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SmallVector<SDValue, 8> Stores;
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for (unsigned Idx=0; Idx < NumElem * SizeRatio; Idx++) {
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// Extract the Ith element.
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SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
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NarrowScalarVT, Tmp3, DAG.getIntPtrConstant(Idx));
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// Bump pointer.
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Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
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DAG.getIntPtrConstant(Stride));
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// Store if, this element is:
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// - First element on big endian, or
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// - Last element on little endian
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if (( TLI.isBigEndian() && (Idx % SizeRatio == 0)) ||
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((!TLI.isBigEndian() && (Idx % SizeRatio == SizeRatio-1)))) {
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SDValue Store = DAG.getStore(Tmp1, dl, Ex, Tmp2,
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ST->getPointerInfo().getWithOffset(Idx*Stride),
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isVolatile, isNonTemporal, Alignment);
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Stores.push_back(Store);
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}
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}
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Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
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&Stores[0], Stores.size());
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break;
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}
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assert(false && "Unable to legalize the vector trunc store!");
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}// is vector
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// TRUNCSTORE:i16 i32 -> STORE i16
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// TRUNCSTORE:i16 i32 -> STORE i16
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