forked from OSchip/llvm-project
[ARM] Add some more missing T1 opcodes for the peephole optimisier
This adds a few extra Thumb1 opcodes to improve the peephole opimisers ability to remove redundant cmp instructions. tADC and tSBC require a small fixup to prevent MOVS being moved past the instruction, giving the wrong flags. Differential Revision: https://reviews.llvm.org/D58281 llvm-svn: 354791
This commit is contained in:
David Green
parent
a066f1f9e6
commit
b504f104b2
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@ -2692,6 +2692,17 @@ static bool isOptimizeCompareCandidate(MachineInstr *MI, bool &IsThumb1) {
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case ARM::tSUBi3:
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case ARM::tSUBi8:
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case ARM::tMUL:
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case ARM::tADC:
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case ARM::tSBC:
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case ARM::tRSB:
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case ARM::tAND:
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case ARM::tORR:
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case ARM::tEOR:
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case ARM::tBIC:
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case ARM::tMVN:
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case ARM::tASRri:
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case ARM::tASRrr:
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case ARM::tROR:
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IsThumb1 = true;
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LLVM_FALLTHROUGH;
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case ARM::RSBrr:
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@ -2814,20 +2825,22 @@ bool ARMBaseInstrInfo::optimizeCompareInstr(
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// CMP. This peephole works on the vregs, so is still in SSA form. As a
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// consequence, the movs won't redefine/kill the MUL operands which would
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// make this reordering illegal.
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const TargetRegisterInfo *TRI = &getRegisterInfo();
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if (MI && IsThumb1) {
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--I;
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bool CanReorder = true;
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const bool HasStmts = I != E;
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for (; I != E; --I) {
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if (I->getOpcode() != ARM::tMOVi8) {
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CanReorder = false;
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break;
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if (I != E && !MI->readsRegister(ARM::CPSR, TRI)) {
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bool CanReorder = true;
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for (; I != E; --I) {
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if (I->getOpcode() != ARM::tMOVi8) {
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CanReorder = false;
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break;
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}
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}
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if (CanReorder) {
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MI = MI->removeFromParent();
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E = CmpInstr;
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CmpInstr.getParent()->insert(E, MI);
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}
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}
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if (HasStmts && CanReorder) {
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MI = MI->removeFromParent();
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E = CmpInstr;
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CmpInstr.getParent()->insert(E, MI);
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}
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I = CmpInstr;
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E = MI;
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@ -2835,7 +2848,6 @@ bool ARMBaseInstrInfo::optimizeCompareInstr(
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// Check that CPSR isn't set between the comparison instruction and the one we
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// want to change. At the same time, search for SubAdd.
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const TargetRegisterInfo *TRI = &getRegisterInfo();
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bool SubAddIsThumb1 = false;
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do {
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const MachineInstr &Instr = *--I;
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@ -29,7 +29,6 @@ tailrecurse: ; preds = %sw.bb, %entry
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; THUMB: movs r[[R0:[0-9]+]], #3
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; THUMB-NEXT: ands r[[R0]], r
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; THUMB-NEXT: cmp r[[R0]], #0
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; THUMB-NEXT: beq
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; T2: ands {{r[0-9]+}}, {{r[0-9]+}}, #3
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@ -0,0 +1,403 @@
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# RUN: llc -mtriple thumbv8m.base-none-eabi -run-pass=peephole-opt -verify-machineinstrs -o - %s | FileCheck %s
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--- |
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv8m.base-none-none-eabi"
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define i32 @test_adc(i32 %a, i32 %b) { ret i32 %a }
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define i32 @test_adc_mov(i32 %a, i32 %b) { ret i32 %a }
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define i32 @test_sbc(i32 %a, i32 %b) { ret i32 %a }
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define i32 @test_rsb(i32 %a) { ret i32 %a }
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define i32 @test_and(i32 %a, i32 %b) { ret i32 %a }
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define i32 @test_orr(i32 %a, i32 %b) { ret i32 %a }
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define i32 @test_eor(i32 %a, i32 %b) { ret i32 %a }
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define i32 @test_bic(i32 %a, i32 %b) { ret i32 %a }
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define i32 @test_mvn(i32 %a) { ret i32 %a }
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define i32 @test_asrrr(i32 %a, i32 %b) { ret i32 %a }
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define i32 @test_asrri(i32 %a) { ret i32 %a }
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define i32 @test_ror(i32 %a, i32 %b) { ret i32 %a }
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...
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---
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name: test_adc
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liveins:
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- { reg: '$r0', virtual-reg: '%0' }
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- { reg: '$r1', virtual-reg: '%1' }
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body: |
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; CHECK-LABEL: name: test_adc
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; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
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; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
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; CHECK: [[tADDrr:%[0-9]+]]:tgpr, $cpsr = tADDrr [[COPY1]], [[COPY]], 14, $noreg
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; CHECK: [[tADC:%[0-9]+]]:tgpr, $cpsr = tADC [[COPY1]], [[COPY]], 14, $noreg, implicit $cpsr
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; CHECK: tBcc %bb.2, 1, $cpsr
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; CHECK: tB %bb.1, 14, $noreg
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bb.0:
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successors: %bb.2(0x40000000), %bb.1(0x40000000)
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liveins: $r0, $r1
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%1:tgpr = COPY $r1
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%0:tgpr = COPY $r0
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%3:tgpr, $cpsr = tADDrr %0, %1, 14, $noreg
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%2:tgpr, dead $cpsr = tADC %0, %1, 14, $noreg, implicit $cpsr
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tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
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tBcc %bb.2, 1, $cpsr
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tB %bb.1, 14, $noreg
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bb.1:
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$r0 = COPY %0
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tBX_RET 14, $noreg, implicit $r0
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bb.2:
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%4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
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$r0 = COPY %2
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tBX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_adc_mov
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liveins:
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- { reg: '$r0', virtual-reg: '%0' }
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- { reg: '$r1', virtual-reg: '%1' }
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body: |
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; CHECK-LABEL: name: test_adc_mov
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; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
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; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
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; CHECK: [[tADDrr:%[0-9]+]]:tgpr, $cpsr = tADDrr [[COPY1]], [[COPY]], 14, $noreg
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; CHECK: [[tADC:%[0-9]+]]:tgpr, dead $cpsr = tADC [[COPY1]], [[COPY]], 14, $noreg, implicit $cpsr
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; CHECK: [[tMOVi8_:%[0-9]+]]:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
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; CHECK: tCMPi8 [[tADC]], 0, 14, $noreg, implicit-def $cpsr
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; CHECK: tBcc %bb.2, 1, $cpsr
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; CHECK: tB %bb.1, 14, $noreg
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bb.0:
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successors: %bb.2(0x40000000), %bb.1(0x40000000)
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liveins: $r0, $r1
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%1:tgpr = COPY $r1
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%0:tgpr = COPY $r0
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%3:tgpr, $cpsr = tADDrr %0, %1, 14, $noreg
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%2:tgpr, dead $cpsr = tADC %0, %1, 14, $noreg, implicit $cpsr
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%5:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
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tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
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tBcc %bb.2, 1, $cpsr
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tB %bb.1, 14, $noreg
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bb.1:
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$r0 = COPY %0
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tBX_RET 14, $noreg, implicit $r0
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bb.2:
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%4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
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$r0 = COPY %2
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tBX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_sbc
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liveins:
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- { reg: '$r0', virtual-reg: '%0' }
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- { reg: '$r1', virtual-reg: '%1' }
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body: |
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; CHECK-LABEL: name: test_sbc
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; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
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; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
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; CHECK: [[tADDrr:%[0-9]+]]:tgpr, $cpsr = tADDrr [[COPY1]], [[COPY]], 14, $noreg
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; CHECK: [[tSBC:%[0-9]+]]:tgpr, $cpsr = tSBC [[COPY1]], [[COPY]], 14, $noreg, implicit $cpsr
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; CHECK: tBcc %bb.2, 1, $cpsr
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; CHECK: tB %bb.1, 14, $noreg
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bb.0:
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successors: %bb.2(0x40000000), %bb.1(0x40000000)
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liveins: $r0, $r1
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%1:tgpr = COPY $r1
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%0:tgpr = COPY $r0
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%3:tgpr, $cpsr = tADDrr %0, %1, 14, $noreg
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%2:tgpr, dead $cpsr = tSBC %0, %1, 14, $noreg, implicit $cpsr
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tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
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tBcc %bb.2, 1, $cpsr
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tB %bb.1, 14, $noreg
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bb.1:
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$r0 = COPY %0
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tBX_RET 14, $noreg, implicit $r0
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bb.2:
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%4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
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$r0 = COPY %2
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tBX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_rsb
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liveins:
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- { reg: '$r0', virtual-reg: '%0' }
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body: |
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; CHECK-LABEL: name: test_rsb
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; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
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; CHECK: [[tRSB:%[0-9]+]]:tgpr, $cpsr = tRSB [[COPY]], 14, $noreg
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; CHECK: tBcc %bb.2, 1, $cpsr
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; CHECK: tB %bb.1, 14, $noreg
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bb.0:
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successors: %bb.2(0x40000000), %bb.1(0x40000000)
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liveins: $r0, $r1
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%0:tgpr = COPY $r0
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%1:tgpr, dead $cpsr = tRSB %0, 14, $noreg
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tCMPi8 %1, 0, 14, $noreg, implicit-def $cpsr
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tBcc %bb.2, 1, $cpsr
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tB %bb.1, 14, $noreg
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bb.1:
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$r0 = COPY %0
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tBX_RET 14, $noreg, implicit $r0
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bb.2:
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%4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
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$r0 = COPY %1
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tBX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_and
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liveins:
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- { reg: '$r0', virtual-reg: '%0' }
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- { reg: '$r1', virtual-reg: '%1' }
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body: |
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; CHECK-LABEL: name: test_and
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; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
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; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
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; CHECK: [[tAND:%[0-9]+]]:tgpr, $cpsr = tAND [[COPY1]], [[COPY]], 14, $noreg
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; CHECK: tBcc %bb.2, 1, $cpsr
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; CHECK: tB %bb.1, 14, $noreg
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bb.0:
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successors: %bb.2(0x40000000), %bb.1(0x40000000)
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liveins: $r0, $r1
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%1:tgpr = COPY $r1
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%0:tgpr = COPY $r0
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%2:tgpr, dead $cpsr = tAND %0, %1, 14, $noreg
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tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
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tBcc %bb.2, 1, $cpsr
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tB %bb.1, 14, $noreg
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bb.1:
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$r0 = COPY %0
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tBX_RET 14, $noreg, implicit $r0
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bb.2:
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%4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
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$r0 = COPY %2
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tBX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_orr
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liveins:
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- { reg: '$r0', virtual-reg: '%0' }
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- { reg: '$r1', virtual-reg: '%1' }
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body: |
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; CHECK-LABEL: name: test_orr
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; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
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; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
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; CHECK: [[tORR:%[0-9]+]]:tgpr, $cpsr = tORR [[COPY1]], [[COPY]], 14, $noreg
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; CHECK: tBcc %bb.2, 1, $cpsr
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; CHECK: tB %bb.1, 14, $noreg
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bb.0:
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successors: %bb.2(0x40000000), %bb.1(0x40000000)
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liveins: $r0, $r1
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%1:tgpr = COPY $r1
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%0:tgpr = COPY $r0
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%2:tgpr, dead $cpsr = tORR %0, %1, 14, $noreg
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tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
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tBcc %bb.2, 1, $cpsr
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tB %bb.1, 14, $noreg
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bb.1:
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$r0 = COPY %0
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tBX_RET 14, $noreg, implicit $r0
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bb.2:
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%4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
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$r0 = COPY %2
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tBX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_eor
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liveins:
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- { reg: '$r0', virtual-reg: '%0' }
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- { reg: '$r1', virtual-reg: '%1' }
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body: |
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; CHECK-LABEL: name: test_eor
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; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
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; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
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; CHECK: [[tEOR:%[0-9]+]]:tgpr, $cpsr = tEOR [[COPY1]], [[COPY]], 14, $noreg
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; CHECK: tBcc %bb.2, 1, $cpsr
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; CHECK: tB %bb.1, 14, $noreg
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bb.0:
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successors: %bb.2(0x40000000), %bb.1(0x40000000)
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liveins: $r0, $r1
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%1:tgpr = COPY $r1
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%0:tgpr = COPY $r0
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%2:tgpr, dead $cpsr = tEOR %0, %1, 14, $noreg
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tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
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tBcc %bb.2, 1, $cpsr
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tB %bb.1, 14, $noreg
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bb.1:
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$r0 = COPY %0
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tBX_RET 14, $noreg, implicit $r0
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bb.2:
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%4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
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$r0 = COPY %2
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tBX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_bic
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liveins:
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- { reg: '$r0', virtual-reg: '%0' }
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- { reg: '$r1', virtual-reg: '%1' }
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body: |
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; CHECK-LABEL: name: test_bic
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; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
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; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
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; CHECK: [[tBIC:%[0-9]+]]:tgpr, $cpsr = tBIC [[COPY1]], [[COPY]], 14, $noreg
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; CHECK: tBcc %bb.2, 1, $cpsr
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; CHECK: tB %bb.1, 14, $noreg
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bb.0:
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successors: %bb.2(0x40000000), %bb.1(0x40000000)
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liveins: $r0, $r1
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%1:tgpr = COPY $r1
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%0:tgpr = COPY $r0
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%2:tgpr, dead $cpsr = tBIC %0, %1, 14, $noreg
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tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
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tBcc %bb.2, 1, $cpsr
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tB %bb.1, 14, $noreg
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bb.1:
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$r0 = COPY %0
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tBX_RET 14, $noreg, implicit $r0
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bb.2:
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%4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
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$r0 = COPY %2
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tBX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_mvn
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liveins:
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- { reg: '$r0', virtual-reg: '%0' }
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body: |
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; CHECK-LABEL: name: test_mvn
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; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
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; CHECK: [[tMVN:%[0-9]+]]:tgpr, $cpsr = tMVN [[COPY]], 14, $noreg
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; CHECK: tBcc %bb.2, 1, $cpsr
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; CHECK: tB %bb.1, 14, $noreg
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bb.0:
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successors: %bb.2(0x40000000), %bb.1(0x40000000)
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liveins: $r0, $r1
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%0:tgpr = COPY $r0
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%1:tgpr, dead $cpsr = tMVN %0, 14, $noreg
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tCMPi8 %1, 0, 14, $noreg, implicit-def $cpsr
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tBcc %bb.2, 1, $cpsr
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tB %bb.1, 14, $noreg
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bb.1:
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$r0 = COPY %0
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tBX_RET 14, $noreg, implicit $r0
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bb.2:
|
||||
%4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
|
||||
$r0 = COPY %1
|
||||
tBX_RET 14, $noreg, implicit $r0
|
||||
...
|
||||
---
|
||||
name: test_asrrr
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '%0' }
|
||||
- { reg: '$r1', virtual-reg: '%1' }
|
||||
body: |
|
||||
; CHECK-LABEL: name: test_asrrr
|
||||
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
|
||||
; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
|
||||
; CHECK: [[tASRrr:%[0-9]+]]:tgpr, $cpsr = tASRrr [[COPY1]], [[COPY]], 14, $noreg
|
||||
; CHECK: tBcc %bb.2, 1, $cpsr
|
||||
; CHECK: tB %bb.1, 14, $noreg
|
||||
bb.0:
|
||||
successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
liveins: $r0, $r1
|
||||
|
||||
%1:tgpr = COPY $r1
|
||||
%0:tgpr = COPY $r0
|
||||
%2:tgpr, dead $cpsr = tASRrr %0, %1, 14, $noreg
|
||||
tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
|
||||
tBcc %bb.2, 1, $cpsr
|
||||
tB %bb.1, 14, $noreg
|
||||
|
||||
bb.1:
|
||||
$r0 = COPY %0
|
||||
tBX_RET 14, $noreg, implicit $r0
|
||||
|
||||
bb.2:
|
||||
%4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
|
||||
$r0 = COPY %2
|
||||
tBX_RET 14, $noreg, implicit $r0
|
||||
...
|
||||
---
|
||||
name: test_asrri
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '%0' }
|
||||
body: |
|
||||
; CHECK-LABEL: name: test_asrri
|
||||
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
|
||||
; CHECK: [[tASRri:%[0-9]+]]:tgpr, $cpsr = tASRri [[COPY]], 1, 14, $noreg
|
||||
; CHECK: tBcc %bb.2, 1, $cpsr
|
||||
; CHECK: tB %bb.1, 14, $noreg
|
||||
bb.0:
|
||||
successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
liveins: $r0, $r1
|
||||
|
||||
%0:tgpr = COPY $r0
|
||||
%2:tgpr, dead $cpsr = tASRri %0, 1, 14, $noreg
|
||||
tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
|
||||
tBcc %bb.2, 1, $cpsr
|
||||
tB %bb.1, 14, $noreg
|
||||
|
||||
bb.1:
|
||||
$r0 = COPY %0
|
||||
tBX_RET 14, $noreg, implicit $r0
|
||||
|
||||
bb.2:
|
||||
%4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
|
||||
$r0 = COPY %2
|
||||
tBX_RET 14, $noreg, implicit $r0
|
||||
...
|
||||
---
|
||||
name: test_ror
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '%0' }
|
||||
- { reg: '$r1', virtual-reg: '%1' }
|
||||
body: |
|
||||
; CHECK-LABEL: name: test_ror
|
||||
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
|
||||
; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
|
||||
; CHECK: [[tROR:%[0-9]+]]:tgpr, $cpsr = tROR [[COPY1]], [[COPY]], 14, $noreg
|
||||
; CHECK: tBcc %bb.2, 1, $cpsr
|
||||
; CHECK: tB %bb.1, 14, $noreg
|
||||
bb.0:
|
||||
successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
liveins: $r0, $r1
|
||||
|
||||
%1:tgpr = COPY $r1
|
||||
%0:tgpr = COPY $r0
|
||||
%2:tgpr, dead $cpsr = tROR %0, %1, 14, $noreg
|
||||
tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
|
||||
tBcc %bb.2, 1, $cpsr
|
||||
tB %bb.1, 14, $noreg
|
||||
|
||||
bb.1:
|
||||
$r0 = COPY %0
|
||||
tBX_RET 14, $noreg, implicit $r0
|
||||
|
||||
bb.2:
|
||||
%4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
|
||||
$r0 = COPY %2
|
||||
tBX_RET 14, $noreg, implicit $r0
|
||||
...
|
||||
|
|
@ -45,7 +45,7 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
|
|||
; THUMBV6-NEXT: mov r2, r7
|
||||
; THUMBV6-NEXT: mov r3, r5
|
||||
; THUMBV6-NEXT: bl __aeabi_lmul
|
||||
; THUMBV6-NEXT: str r1, [sp, #28] @ 4-byte Spill
|
||||
; THUMBV6-NEXT: str r1, [sp, #24] @ 4-byte Spill
|
||||
; THUMBV6-NEXT: adds r6, r0, r6
|
||||
; THUMBV6-NEXT: str r4, [sp, #68] @ 4-byte Spill
|
||||
; THUMBV6-NEXT: mov r0, r4
|
||||
|
|
@ -58,28 +58,28 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
|
|||
; THUMBV6-NEXT: str r0, [sp, #16] @ 4-byte Spill
|
||||
; THUMBV6-NEXT: mov r0, r5
|
||||
; THUMBV6-NEXT: adcs r0, r5
|
||||
; THUMBV6-NEXT: str r0, [sp, #64] @ 4-byte Spill
|
||||
; THUMBV6-NEXT: ldr r7, [sp, #104]
|
||||
; THUMBV6-NEXT: str r0, [sp, #60] @ 4-byte Spill
|
||||
; THUMBV6-NEXT: ldr r4, [sp, #104]
|
||||
; THUMBV6-NEXT: ldr r0, [sp, #72] @ 4-byte Reload
|
||||
; THUMBV6-NEXT: mov r1, r5
|
||||
; THUMBV6-NEXT: mov r2, r7
|
||||
; THUMBV6-NEXT: mov r2, r4
|
||||
; THUMBV6-NEXT: mov r3, r5
|
||||
; THUMBV6-NEXT: bl __aeabi_lmul
|
||||
; THUMBV6-NEXT: mov r6, r0
|
||||
; THUMBV6-NEXT: str r1, [sp, #52] @ 4-byte Spill
|
||||
; THUMBV6-NEXT: ldr r0, [sp, #108]
|
||||
; THUMBV6-NEXT: str r0, [sp, #60] @ 4-byte Spill
|
||||
; THUMBV6-NEXT: str r0, [sp, #32] @ 4-byte Spill
|
||||
; THUMBV6-NEXT: mov r1, r5
|
||||
; THUMBV6-NEXT: ldr r4, [sp, #44] @ 4-byte Reload
|
||||
; THUMBV6-NEXT: mov r2, r4
|
||||
; THUMBV6-NEXT: ldr r7, [sp, #44] @ 4-byte Reload
|
||||
; THUMBV6-NEXT: mov r2, r7
|
||||
; THUMBV6-NEXT: mov r3, r5
|
||||
; THUMBV6-NEXT: bl __aeabi_lmul
|
||||
; THUMBV6-NEXT: str r1, [sp, #32] @ 4-byte Spill
|
||||
; THUMBV6-NEXT: str r1, [sp, #28] @ 4-byte Spill
|
||||
; THUMBV6-NEXT: adds r6, r0, r6
|
||||
; THUMBV6-NEXT: str r7, [sp, #24] @ 4-byte Spill
|
||||
; THUMBV6-NEXT: mov r0, r7
|
||||
; THUMBV6-NEXT: str r4, [sp, #64] @ 4-byte Spill
|
||||
; THUMBV6-NEXT: mov r0, r4
|
||||
; THUMBV6-NEXT: mov r1, r5
|
||||
; THUMBV6-NEXT: mov r2, r4
|
||||
; THUMBV6-NEXT: mov r2, r7
|
||||
; THUMBV6-NEXT: mov r3, r5
|
||||
; THUMBV6-NEXT: bl __aeabi_lmul
|
||||
; THUMBV6-NEXT: adds r1, r1, r6
|
||||
|
|
@ -97,7 +97,7 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
|
|||
; THUMBV6-NEXT: ldr r0, [sp, #40] @ 4-byte Reload
|
||||
; THUMBV6-NEXT: adcs r1, r0
|
||||
; THUMBV6-NEXT: str r1, [r2, #12]
|
||||
; THUMBV6-NEXT: ldr r1, [sp, #28] @ 4-byte Reload
|
||||
; THUMBV6-NEXT: ldr r1, [sp, #24] @ 4-byte Reload
|
||||
; THUMBV6-NEXT: adcs r5, r5
|
||||
; THUMBV6-NEXT: movs r0, #1
|
||||
; THUMBV6-NEXT: cmp r1, #0
|
||||
|
|
@ -118,42 +118,43 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
|
|||
; THUMBV6-NEXT: cmp r1, #0
|
||||
; THUMBV6-NEXT: mov r2, r0
|
||||
; THUMBV6-NEXT: ldr r3, [sp, #48] @ 4-byte Reload
|
||||
; THUMBV6-NEXT: ldr r6, [sp, #32] @ 4-byte Reload
|
||||
; THUMBV6-NEXT: ldr r7, [sp, #28] @ 4-byte Reload
|
||||
; THUMBV6-NEXT: bne .LBB0_6
|
||||
; THUMBV6-NEXT: @ %bb.5: @ %start
|
||||
; THUMBV6-NEXT: ldr r2, [sp, #80] @ 4-byte Reload
|
||||
; THUMBV6-NEXT: .LBB0_6: @ %start
|
||||
; THUMBV6-NEXT: cmp r3, #0
|
||||
; THUMBV6-NEXT: mov r7, r0
|
||||
; THUMBV6-NEXT: mov r6, r0
|
||||
; THUMBV6-NEXT: ldr r1, [sp, #72] @ 4-byte Reload
|
||||
; THUMBV6-NEXT: bne .LBB0_8
|
||||
; THUMBV6-NEXT: @ %bb.7: @ %start
|
||||
; THUMBV6-NEXT: mov r7, r3
|
||||
; THUMBV6-NEXT: mov r6, r3
|
||||
; THUMBV6-NEXT: .LBB0_8: @ %start
|
||||
; THUMBV6-NEXT: cmp r6, #0
|
||||
; THUMBV6-NEXT: str r6, [sp, #56] @ 4-byte Spill
|
||||
; THUMBV6-NEXT: ldr r6, [sp, #32] @ 4-byte Reload
|
||||
; THUMBV6-NEXT: cmp r7, #0
|
||||
; THUMBV6-NEXT: mov r3, r0
|
||||
; THUMBV6-NEXT: bne .LBB0_10
|
||||
; THUMBV6-NEXT: @ %bb.9: @ %start
|
||||
; THUMBV6-NEXT: mov r3, r6
|
||||
; THUMBV6-NEXT: mov r3, r7
|
||||
; THUMBV6-NEXT: .LBB0_10: @ %start
|
||||
; THUMBV6-NEXT: cmp r1, #0
|
||||
; THUMBV6-NEXT: mov r6, r1
|
||||
; THUMBV6-NEXT: mov r7, r1
|
||||
; THUMBV6-NEXT: mov r1, r0
|
||||
; THUMBV6-NEXT: bne .LBB0_12
|
||||
; THUMBV6-NEXT: @ %bb.11: @ %start
|
||||
; THUMBV6-NEXT: mov r1, r6
|
||||
; THUMBV6-NEXT: mov r1, r7
|
||||
; THUMBV6-NEXT: .LBB0_12: @ %start
|
||||
; THUMBV6-NEXT: str r7, [sp, #72] @ 4-byte Spill
|
||||
; THUMBV6-NEXT: ands r2, r4
|
||||
; THUMBV6-NEXT: ldr r6, [sp, #60] @ 4-byte Reload
|
||||
; THUMBV6-NEXT: mov r7, r6
|
||||
; THUMBV6-NEXT: cmp r6, #0
|
||||
; THUMBV6-NEXT: mov r4, r0
|
||||
; THUMBV6-NEXT: bne .LBB0_14
|
||||
; THUMBV6-NEXT: @ %bb.13: @ %start
|
||||
; THUMBV6-NEXT: mov r4, r6
|
||||
; THUMBV6-NEXT: mov r4, r7
|
||||
; THUMBV6-NEXT: .LBB0_14: @ %start
|
||||
; THUMBV6-NEXT: ldr r7, [sp, #40] @ 4-byte Reload
|
||||
; THUMBV6-NEXT: orrs r2, r7
|
||||
; THUMBV6-NEXT: ldr r6, [sp, #40] @ 4-byte Reload
|
||||
; THUMBV6-NEXT: orrs r2, r6
|
||||
; THUMBV6-NEXT: ands r4, r1
|
||||
; THUMBV6-NEXT: orrs r4, r3
|
||||
; THUMBV6-NEXT: ldr r3, [sp, #52] @ 4-byte Reload
|
||||
|
|
@ -163,26 +164,23 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
|
|||
; THUMBV6-NEXT: @ %bb.15: @ %start
|
||||
; THUMBV6-NEXT: mov r1, r3
|
||||
; THUMBV6-NEXT: .LBB0_16: @ %start
|
||||
; THUMBV6-NEXT: ldr r3, [sp, #72] @ 4-byte Reload
|
||||
; THUMBV6-NEXT: ldr r3, [sp, #56] @ 4-byte Reload
|
||||
; THUMBV6-NEXT: orrs r2, r3
|
||||
; THUMBV6-NEXT: orrs r4, r1
|
||||
; THUMBV6-NEXT: ldr r1, [sp, #68] @ 4-byte Reload
|
||||
; THUMBV6-NEXT: ldr r3, [sp, #80] @ 4-byte Reload
|
||||
; THUMBV6-NEXT: orrs r1, r3
|
||||
; THUMBV6-NEXT: cmp r1, #0
|
||||
; THUMBV6-NEXT: mov r3, r0
|
||||
; THUMBV6-NEXT: bne .LBB0_18
|
||||
; THUMBV6-NEXT: @ %bb.17: @ %start
|
||||
; THUMBV6-NEXT: mov r3, r1
|
||||
; THUMBV6-NEXT: .LBB0_18: @ %start
|
||||
; THUMBV6-NEXT: ldr r1, [sp, #64] @ 4-byte Reload
|
||||
; THUMBV6-NEXT: ldr r1, [sp, #60] @ 4-byte Reload
|
||||
; THUMBV6-NEXT: orrs r2, r1
|
||||
; THUMBV6-NEXT: ldr r1, [sp, #44] @ 4-byte Reload
|
||||
; THUMBV6-NEXT: orrs r4, r1
|
||||
; THUMBV6-NEXT: ldr r1, [sp, #24] @ 4-byte Reload
|
||||
; THUMBV6-NEXT: orrs r1, r6
|
||||
; THUMBV6-NEXT: mov r6, r1
|
||||
; THUMBV6-NEXT: cmp r1, #0
|
||||
; THUMBV6-NEXT: ldr r6, [sp, #64] @ 4-byte Reload
|
||||
; THUMBV6-NEXT: orrs r6, r7
|
||||
; THUMBV6-NEXT: mov r1, r0
|
||||
; THUMBV6-NEXT: bne .LBB0_20
|
||||
; THUMBV6-NEXT: @ %bb.19: @ %start
|
||||
|
|
|
|||
Loading…
Reference in New Issue