From b4a1d8a84ce0a825cb31f602e11913d06f69faf2 Mon Sep 17 00:00:00 2001 From: Roman Lebedev Date: Mon, 23 Sep 2019 17:04:14 +0000 Subject: [PATCH] [InstCombine] dropRedundantMaskingOfLeftShiftInput(): pat. a/b with mask (PR42563) Summary: And this is **finally** the interesting part of that fold! If we have a pattern `(x & (~(-1 << maskNbits))) << shiftNbits`, we already know (have a fold) that will drop the `& (~(-1 << maskNbits))` mask iff `(maskNbits+shiftNbits) u>= bitwidth(x)`. But that is actually ignorant, there's more general fold here: In this pattern, `(maskNbits+shiftNbits)` actually correlates with the number of low bits that will remain in the final value. So even if `(maskNbits+shiftNbits) u< bitwidth(x)`, we can still fold, we will just need to apply a **constant** mask afterwards: ``` Name: a, normal+mask %onebit = shl i32 -1, C1 %mask = xor i32 %onebit, -1 %masked = and i32 %mask, %x %r = shl i32 %masked, C2 => %n0 = shl i32 %x, C2 %n1 = add i32 C1, C2 %n2 = zext i32 %n1 to i64 %n3 = shl i64 -1, %n2 %n4 = xor i64 %n3, -1 %n5 = trunc i64 %n4 to i32 %r = and i32 %n0, %n5 ``` https://rise4fun.com/Alive/F5R Naturally, old `%masked` will have to be one-use. Similar fold exists for patterns c,d,e, will post patch later. https://bugs.llvm.org/show_bug.cgi?id=42563 Reviewers: spatel, nikic, xbolva00 Reviewed By: spatel Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67677 llvm-svn: 372629 --- .../InstCombine/InstCombineShifts.cpp | 33 +++++++++++++++++-- ...dant-left-shift-input-masking-variant-a.ll | 12 +++---- ...dant-left-shift-input-masking-variant-b.ll | 12 +++---- 3 files changed, 42 insertions(+), 15 deletions(-) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp index fee95927cd25..3f466495c5e7 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp @@ -152,6 +152,7 @@ dropRedundantMaskingOfLeftShiftInput(BinaryOperator *OuterShift, m_Shr(m_Shl(m_AllOnes(), m_Value(MaskShAmt)), m_Deferred(MaskShAmt)); Value *X; + Constant *NewMask; if (match(Masked, m_c_And(m_CombineOr(MaskA, MaskB), m_Value(X)))) { // Can we simplify (MaskShAmt+ShiftShAmt) ? auto *SumOfShAmts = dyn_cast_or_null( @@ -166,8 +167,27 @@ dropRedundantMaskingOfLeftShiftInput(BinaryOperator *OuterShift, // bitwidth, we'll need to also produce a mask to keep SumOfShAmts low bits. // So, does *any* channel need a mask? if (!match(SumOfShAmts, m_SpecificInt_ICMP(ICmpInst::Predicate::ICMP_UGE, - APInt(BitWidth, BitWidth)))) - return nullptr; // FIXME. + APInt(BitWidth, BitWidth)))) { + // But for a mask we need to get rid of old masking instruction. + if (!Masked->hasOneUse()) + return nullptr; // Else we can't perform the fold. + // We should produce compute the mask in wider type, and truncate later! + // Get type twice as wide element-wise (same number of elements!). + Type *ExtendedScalarTy = Type::getIntNTy(Ty->getContext(), 2 * BitWidth); + Type *ExtendedTy = + Ty->isVectorTy() + ? VectorType::get(ExtendedScalarTy, Ty->getVectorNumElements()) + : ExtendedScalarTy; + auto *ExtendedSumOfShAmts = + ConstantExpr::getZExt(SumOfShAmts, ExtendedTy); + // And compute the mask as usual: ~(-1 << (SumOfShAmts)) + auto *ExtendedAllOnes = ConstantExpr::getAllOnesValue(ExtendedTy); + auto *ExtendedInvertedMask = + ConstantExpr::getShl(ExtendedAllOnes, ExtendedSumOfShAmts); + auto *ExtendedMask = ConstantExpr::getNot(ExtendedInvertedMask); + NewMask = ConstantExpr::getTrunc(ExtendedMask, Ty); + } else + NewMask = nullptr; // No mask needed. // All good, we can do this fold. } else if (match(Masked, m_c_And(m_CombineOr(MaskC, MaskD), m_Value(X))) || match(Masked, m_Shr(m_Shl(m_Value(X), m_Value(MaskShAmt)), @@ -185,12 +205,19 @@ dropRedundantMaskingOfLeftShiftInput(BinaryOperator *OuterShift, if (!match(ShAmtsDiff, m_NonNegative())) return nullptr; // FIXME. // All good, we can do this fold. + NewMask = nullptr; // No mask needed. } else return nullptr; // Don't know anything about this pattern. // No 'NUW'/'NSW'! // We no longer know that we won't shift-out non-0 bits. - return BinaryOperator::Create(OuterShift->getOpcode(), X, ShiftShAmt); + auto *NewShift = + BinaryOperator::Create(OuterShift->getOpcode(), X, ShiftShAmt); + if (!NewMask) + return NewShift; + + Builder.Insert(NewShift); + return BinaryOperator::Create(Instruction::And, NewShift, NewMask); } Instruction *InstCombiner::commonShiftTransforms(BinaryOperator &I) { diff --git a/llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-a.ll b/llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-a.ll index 6a944cf95096..5445275ad1c7 100644 --- a/llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-a.ll +++ b/llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-a.ll @@ -18,13 +18,13 @@ define i32 @t0_basic(i32 %x, i32 %nbits) { ; CHECK-NEXT: [[T0:%.*]] = add i32 [[NBITS:%.*]], -1 ; CHECK-NEXT: [[T1:%.*]] = shl i32 1, [[T0]] ; CHECK-NEXT: [[T2:%.*]] = add i32 [[T1]], -1 -; CHECK-NEXT: [[T3:%.*]] = and i32 [[T2]], [[X:%.*]] ; CHECK-NEXT: [[T4:%.*]] = sub i32 32, [[NBITS]] ; CHECK-NEXT: call void @use32(i32 [[T0]]) ; CHECK-NEXT: call void @use32(i32 [[T1]]) ; CHECK-NEXT: call void @use32(i32 [[T2]]) ; CHECK-NEXT: call void @use32(i32 [[T4]]) -; CHECK-NEXT: [[T5:%.*]] = shl i32 [[T3]], [[T4]] +; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], [[T4]] +; CHECK-NEXT: [[T5:%.*]] = and i32 [[TMP1]], 2147483647 ; CHECK-NEXT: ret i32 [[T5]] ; %t0 = add i32 %nbits, -1 @@ -49,13 +49,13 @@ define <8 x i32> @t1_vec_splat(<8 x i32> %x, <8 x i32> %nbits) { ; CHECK-NEXT: [[T0:%.*]] = add <8 x i32> [[NBITS:%.*]], ; CHECK-NEXT: [[T1:%.*]] = shl <8 x i32> , [[T0]] ; CHECK-NEXT: [[T2:%.*]] = add <8 x i32> [[T1]], -; CHECK-NEXT: [[T3:%.*]] = and <8 x i32> [[T2]], [[X:%.*]] ; CHECK-NEXT: [[T4:%.*]] = sub <8 x i32> , [[NBITS]] ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]]) ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T1]]) ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]]) ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T4]]) -; CHECK-NEXT: [[T5:%.*]] = shl <8 x i32> [[T3]], [[T4]] +; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> [[X:%.*]], [[T4]] +; CHECK-NEXT: [[T5:%.*]] = and <8 x i32> [[TMP1]], ; CHECK-NEXT: ret <8 x i32> [[T5]] ; %t0 = add <8 x i32> %nbits, @@ -76,13 +76,13 @@ define <8 x i32> @t2_vec_nonsplat(<8 x i32> %x, <8 x i32> %nbits) { ; CHECK-NEXT: [[T0:%.*]] = add <8 x i32> [[NBITS:%.*]], ; CHECK-NEXT: [[T1:%.*]] = shl <8 x i32> , [[T0]] ; CHECK-NEXT: [[T2:%.*]] = add <8 x i32> [[T1]], -; CHECK-NEXT: [[T3:%.*]] = and <8 x i32> [[T2]], [[X:%.*]] ; CHECK-NEXT: [[T4:%.*]] = sub <8 x i32> , [[NBITS]] ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]]) ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T1]]) ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]]) ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T4]]) -; CHECK-NEXT: [[T5:%.*]] = shl <8 x i32> [[T3]], [[T4]] +; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> [[X:%.*]], [[T4]] +; CHECK-NEXT: [[T5:%.*]] = and <8 x i32> [[TMP1]], ; CHECK-NEXT: ret <8 x i32> [[T5]] ; %t0 = add <8 x i32> %nbits, diff --git a/llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-b.ll b/llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-b.ll index 784de8bc7181..6165b5796614 100644 --- a/llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-b.ll +++ b/llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-b.ll @@ -18,13 +18,13 @@ define i32 @t0_basic(i32 %x, i32 %nbits) { ; CHECK-NEXT: [[T0:%.*]] = add i32 [[NBITS:%.*]], -1 ; CHECK-NEXT: [[T1:%.*]] = shl i32 -1, [[T0]] ; CHECK-NEXT: [[T2:%.*]] = xor i32 [[T1]], -1 -; CHECK-NEXT: [[T3:%.*]] = and i32 [[T2]], [[X:%.*]] ; CHECK-NEXT: [[T4:%.*]] = sub i32 32, [[NBITS]] ; CHECK-NEXT: call void @use32(i32 [[T0]]) ; CHECK-NEXT: call void @use32(i32 [[T1]]) ; CHECK-NEXT: call void @use32(i32 [[T2]]) ; CHECK-NEXT: call void @use32(i32 [[T4]]) -; CHECK-NEXT: [[T5:%.*]] = shl i32 [[T3]], [[T4]] +; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], [[T4]] +; CHECK-NEXT: [[T5:%.*]] = and i32 [[TMP1]], 2147483647 ; CHECK-NEXT: ret i32 [[T5]] ; %t0 = add i32 %nbits, -1 @@ -49,13 +49,13 @@ define <8 x i32> @t1_vec_splat(<8 x i32> %x, <8 x i32> %nbits) { ; CHECK-NEXT: [[T0:%.*]] = add <8 x i32> [[NBITS:%.*]], ; CHECK-NEXT: [[T1:%.*]] = shl <8 x i32> , [[T0]] ; CHECK-NEXT: [[T2:%.*]] = xor <8 x i32> [[T1]], -; CHECK-NEXT: [[T3:%.*]] = and <8 x i32> [[T2]], [[X:%.*]] ; CHECK-NEXT: [[T4:%.*]] = sub <8 x i32> , [[NBITS]] ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]]) ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T1]]) ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]]) ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T4]]) -; CHECK-NEXT: [[T5:%.*]] = shl <8 x i32> [[T3]], [[T4]] +; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> [[X:%.*]], [[T4]] +; CHECK-NEXT: [[T5:%.*]] = and <8 x i32> [[TMP1]], ; CHECK-NEXT: ret <8 x i32> [[T5]] ; %t0 = add <8 x i32> %nbits, @@ -76,13 +76,13 @@ define <8 x i32> @t2_vec_nonsplat(<8 x i32> %x, <8 x i32> %nbits) { ; CHECK-NEXT: [[T0:%.*]] = add <8 x i32> [[NBITS:%.*]], ; CHECK-NEXT: [[T1:%.*]] = shl <8 x i32> , [[T0]] ; CHECK-NEXT: [[T2:%.*]] = xor <8 x i32> [[T1]], -; CHECK-NEXT: [[T3:%.*]] = and <8 x i32> [[T2]], [[X:%.*]] ; CHECK-NEXT: [[T4:%.*]] = sub <8 x i32> , [[NBITS]] ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]]) ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T1]]) ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]]) ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T4]]) -; CHECK-NEXT: [[T5:%.*]] = shl <8 x i32> [[T3]], [[T4]] +; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> [[X:%.*]], [[T4]] +; CHECK-NEXT: [[T5:%.*]] = and <8 x i32> [[TMP1]], ; CHECK-NEXT: ret <8 x i32> [[T5]] ; %t0 = add <8 x i32> %nbits,