forked from OSchip/llvm-project
parent
15db390f8f
commit
b49b736519
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@ -4,7 +4,7 @@
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; (note: we convert back to i32 to return)
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define ptx_device i32 @cvt_pred_i16(i16 %x, i1 %y) {
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; CHECK: setp.gt.b16 p[[P0:[0-9]+]], rh{{[0-9]+}}, 0
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; CHECK: setp.gt.u16 p[[P0:[0-9]+]], rh{{[0-9]+}}, 0
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; CHECK-NEXT: and.pred p0, p[[P0:[0-9]+]], p{{[0-9]+}};
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; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0:[0-9]+]];
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; CHECK-NEXT: ret;
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@ -15,7 +15,7 @@ define ptx_device i32 @cvt_pred_i16(i16 %x, i1 %y) {
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}
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define ptx_device i32 @cvt_pred_i32(i32 %x, i1 %y) {
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; CHECK: setp.gt.b32 p[[P0:[0-9]+]], r{{[0-9]+}}, 0
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; CHECK: setp.gt.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, 0
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; CHECK-NEXT: and.pred p0, p[[P0:[0-9]+]], p{{[0-9]+}};
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; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0:[0-9]+]];
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; CHECK-NEXT: ret;
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@ -26,7 +26,7 @@ define ptx_device i32 @cvt_pred_i32(i32 %x, i1 %y) {
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}
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define ptx_device i32 @cvt_pred_i64(i64 %x, i1 %y) {
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; CHECK: setp.gt.b64 p[[P0:[0-9]+]], rd{{[0-9]+}}, 0
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; CHECK: setp.gt.u64 p[[P0:[0-9]+]], rd{{[0-9]+}}, 0
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; CHECK-NEXT: and.pred p0, p[[P0:[0-9]+]], p{{[0-9]+}};
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; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0:[0-9]+]];
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; CHECK-NEXT: ret;
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@ -37,7 +37,7 @@ define ptx_device i32 @cvt_pred_i64(i64 %x, i1 %y) {
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}
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define ptx_device i32 @cvt_pred_f32(float %x, i1 %y) {
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; CHECK: setp.gt.b32 p[[P0:[0-9]+]], r{{[0-9]+}}, 0
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; CHECK: setp.gt.f32 p[[P0:[0-9]+]], r{{[0-9]+}}, 0
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; CHECK-NEXT: and.pred p0, p[[P0:[0-9]+]], p{{[0-9]+}};
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; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0:[0-9]+]];
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; CHECK-NEXT: ret;
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@ -48,7 +48,7 @@ define ptx_device i32 @cvt_pred_f32(float %x, i1 %y) {
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}
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define ptx_device i32 @cvt_pred_f64(double %x, i1 %y) {
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; CHECK: setp.gt.b64 p[[P0:[0-9]+]], rd{{[0-9]+}}, 0
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; CHECK: setp.gt.f64 p[[P0:[0-9]+]], rd{{[0-9]+}}, 0
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; CHECK-NEXT: and.pred p0, p[[P0:[0-9]+]], p{{[0-9]+}};
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; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0:[0-9]+]];
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; CHECK-NEXT: ret;
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@ -193,7 +193,7 @@ define ptx_device i32 @test_setp_4_op_format_1(i32 %x, i32 %y, i32 %u, i32 %v) {
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}
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define ptx_device i32 @test_setp_4_op_format_2(i32 %x, i32 %y, i32 %w) {
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; CHECK: setp.gt.b32 p[[P0:[0-9]+]], r{{[0-9]+}}, 0;
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; CHECK: setp.gt.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, 0;
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; CHECK-NEXT: setp.eq.and.u32 p[[P0]], r{{[0-9]+}}, r{{[0-9]+}}, !p[[P0]];
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; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
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; CHECK-NEXT: ret;
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