forked from OSchip/llvm-project
[SystemZ] Use LOAD AND TEST to eliminate comparisons against zero
llvm-svn: 187720
This commit is contained in:
Richard Sandiford
parent
c62c64a038
commit
b49a3ab262
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@ -46,6 +46,7 @@ namespace {
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bool runOnMachineFunction(MachineFunction &F);
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private:
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bool convertToLoadAndTest(MachineInstr *MI);
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bool adjustCCMasksForInstr(MachineInstr *MI, MachineInstr *Compare,
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SmallVectorImpl<MachineInstr *> &CCUsers);
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bool optimizeCompareZero(MachineInstr *Compare,
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@ -83,9 +84,34 @@ static bool resultTests(MachineInstr *MI, unsigned Reg, unsigned SubReg) {
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MI->getOperand(0).getSubReg() == SubReg)
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return true;
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switch (MI->getOpcode()) {
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case SystemZ::LR:
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case SystemZ::LGR:
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case SystemZ::LGFR:
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case SystemZ::LTR:
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case SystemZ::LTGR:
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case SystemZ::LTGFR:
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if (MI->getOperand(1).getReg() == Reg &&
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MI->getOperand(1).getSubReg() == SubReg)
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return true;
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}
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return false;
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}
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// If MI is a load instruction, try to convert it into a LOAD AND TEST.
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// Return true on success.
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bool SystemZElimCompare::convertToLoadAndTest(MachineInstr *MI) {
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unsigned Opcode = TII->getLoadAndTest(MI->getOpcode());
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if (!Opcode)
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return false;
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MI->setDesc(TII->get(Opcode));
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MachineInstrBuilder(*MI->getParent()->getParent(), MI)
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.addReg(SystemZ::CC, RegState::ImplicitDefine);
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return true;
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}
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// The CC users in CCUsers are testing the result of a comparison of some
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// value X against zero and we know that any CC value produced by MI
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// would also reflect the value of X. Try to adjust CCUsers so that
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@ -184,17 +210,21 @@ optimizeCompareZero(MachineInstr *Compare,
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unsigned SrcSubReg = Compare->getOperand(0).getSubReg();
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MachineBasicBlock *MBB = Compare->getParent();
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MachineBasicBlock::iterator MBBI = Compare, MBBE = MBB->begin();
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bool SeenUseOfCC = false;
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while (MBBI != MBBE) {
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--MBBI;
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MachineInstr *MI = MBBI;
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if (resultTests(MI, SrcReg, SrcSubReg) &&
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adjustCCMasksForInstr(MI, Compare, CCUsers)) {
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((!SeenUseOfCC && convertToLoadAndTest(MI)) ||
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adjustCCMasksForInstr(MI, Compare, CCUsers))) {
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EliminatedComparisons += 1;
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return true;
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}
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if (MI->modifiesRegister(SrcReg, TRI) ||
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MI->modifiesRegister(SystemZ::CC, TRI))
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return false;
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if (MI->readsRegister(SystemZ::CC, TRI))
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SeenUseOfCC = true;
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}
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return false;
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}
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@ -753,6 +753,19 @@ unsigned SystemZInstrInfo::getOpcodeForOffset(unsigned Opcode,
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return 0;
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}
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unsigned SystemZInstrInfo::getLoadAndTest(unsigned Opcode) const {
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switch (Opcode) {
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case SystemZ::L: return SystemZ::LT;
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case SystemZ::LY: return SystemZ::LT;
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case SystemZ::LG: return SystemZ::LTG;
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case SystemZ::LGF: return SystemZ::LTGF;
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case SystemZ::LR: return SystemZ::LTR;
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case SystemZ::LGFR: return SystemZ::LTGFR;
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case SystemZ::LGR: return SystemZ::LTGR;
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default: return 0;
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}
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}
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// Return true if Mask matches the regexp 0*1+0*, given that zero masks
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// have already been filtered out. Store the first set bit in LSB and
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// the number of set bits in Length if so.
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@ -193,6 +193,10 @@ public:
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// exists.
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unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const;
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// If Opcode is a load instruction that has a LOAD AND TEST form,
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// return the opcode for the testing form, otherwise return 0.
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unsigned getLoadAndTest(unsigned Opcode) const;
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// Return true if ROTATE AND ... SELECTED BITS can be used to select bits
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// Mask of the R2 operand, given that only the low BitSize bits of Mask are
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// significant. Set Start and End to the I3 and I4 operands if so.
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@ -574,3 +574,226 @@ store:
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exit:
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ret void
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}
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; Test that L gets converted to LT where useful.
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define i32 @f29(i64 %base, i64 %index, i32 *%dest) {
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; CHECK-LABEL: f29:
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; CHECK: lt %r2, 0({{%r2,%r3|%r3,%r2}})
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; CHECK-NEXT: jle .L{{.*}}
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; CHECK: br %r14
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entry:
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%add = add i64 %base, %index
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%ptr = inttoptr i64 %add to i32 *
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%res = load i32 *%ptr
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%cmp = icmp sle i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %res, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; Test that LY gets converted to LT where useful.
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define i32 @f30(i64 %base, i64 %index, i32 *%dest) {
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; CHECK-LABEL: f30:
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; CHECK: lt %r2, 100000({{%r2,%r3|%r3,%r2}})
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; CHECK-NEXT: jle .L{{.*}}
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; CHECK: br %r14
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entry:
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%add1 = add i64 %base, %index
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%add2 = add i64 %add1, 100000
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%ptr = inttoptr i64 %add2 to i32 *
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%res = load i32 *%ptr
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%cmp = icmp sle i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %res, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; Test that LG gets converted to LTG where useful.
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define i64 @f31(i64 %base, i64 %index, i64 *%dest) {
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; CHECK-LABEL: f31:
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; CHECK: ltg %r2, 0({{%r2,%r3|%r3,%r2}})
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; CHECK-NEXT: jhe .L{{.*}}
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; CHECK: br %r14
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entry:
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%add = add i64 %base, %index
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%ptr = inttoptr i64 %add to i64 *
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%res = load i64 *%ptr
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%cmp = icmp sge i64 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i64 %res, i64 *%dest
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br label %exit
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exit:
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ret i64 %res
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}
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; Test that LGF gets converted to LTGF where useful.
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define i64 @f32(i64 %base, i64 %index, i64 *%dest) {
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; CHECK-LABEL: f32:
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; CHECK: ltgf %r2, 0({{%r2,%r3|%r3,%r2}})
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; CHECK-NEXT: jh .L{{.*}}
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; CHECK: br %r14
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entry:
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%add = add i64 %base, %index
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%ptr = inttoptr i64 %add to i32 *
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%val = load i32 *%ptr
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%res = sext i32 %val to i64
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%cmp = icmp sgt i64 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i64 %res, i64 *%dest
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br label %exit
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exit:
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ret i64 %res
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}
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; Test that LR gets converted to LTR where useful.
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define i32 @f33(i32 %dummy, i32 %val, i32 *%dest) {
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; CHECK-LABEL: f33:
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; CHECK: ltr %r2, %r3
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; CHECK-NEXT: #APP
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; CHECK-NEXT: blah %r2
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: jl .L{{.*}}
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; CHECK: br %r14
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entry:
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call void asm sideeffect "blah $0", "{r2}"(i32 %val)
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%cmp = icmp slt i32 %val, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %val, i32 *%dest
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br label %exit
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exit:
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ret i32 %val
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}
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; Test that LGR gets converted to LTGR where useful.
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define i64 @f34(i64 %dummy, i64 %val, i64 *%dest) {
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; CHECK-LABEL: f34:
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; CHECK: ltgr %r2, %r3
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; CHECK-NEXT: #APP
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; CHECK-NEXT: blah %r2
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: jh .L{{.*}}
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; CHECK: br %r14
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entry:
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call void asm sideeffect "blah $0", "{r2}"(i64 %val)
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%cmp = icmp sgt i64 %val, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i64 %val, i64 *%dest
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br label %exit
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exit:
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ret i64 %val
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}
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; Test that LGFR gets converted to LTGFR where useful.
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define i64 @f35(i64 %dummy, i32 %val, i64 *%dest) {
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; CHECK-LABEL: f35:
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; CHECK: ltgfr %r2, %r3
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; CHECK-NEXT: #APP
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; CHECK-NEXT: blah %r2
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: jh .L{{.*}}
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; CHECK: br %r14
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entry:
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%ext = sext i32 %val to i64
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call void asm sideeffect "blah $0", "{r2}"(i64 %ext)
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%cmp = icmp sgt i64 %ext, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i64 %ext, i64 *%dest
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br label %exit
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exit:
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ret i64 %ext
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}
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; Test a case where it is the source rather than destination of LR that
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; we need.
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define i32 @f36(i32 %val, i32 %dummy, i32 *%dest) {
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; CHECK-LABEL: f36:
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; CHECK: ltr %r3, %r2
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; CHECK-NEXT: #APP
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; CHECK-NEXT: blah %r3
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: jl .L{{.*}}
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; CHECK: br %r14
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entry:
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call void asm sideeffect "blah $0", "{r3}"(i32 %val)
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%cmp = icmp slt i32 %val, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %val, i32 *%dest
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br label %exit
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exit:
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ret i32 %val
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}
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; Test a case where it is the source rather than destination of LGR that
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; we need.
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define i64 @f37(i64 %val, i64 %dummy, i64 *%dest) {
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; CHECK-LABEL: f37:
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; CHECK: ltgr %r3, %r2
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; CHECK-NEXT: #APP
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; CHECK-NEXT: blah %r3
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: jl .L{{.*}}
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; CHECK: br %r14
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entry:
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call void asm sideeffect "blah $0", "{r3}"(i64 %val)
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%cmp = icmp slt i64 %val, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i64 %val, i64 *%dest
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br label %exit
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exit:
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ret i64 %val
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}
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; Test a case where it is the source rather than destination of LGFR that
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; we need.
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define i32 @f38(i32 %val, i64 %dummy, i32 *%dest) {
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; CHECK-LABEL: f38:
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; CHECK: ltgfr %r3, %r2
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; CHECK-NEXT: #APP
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; CHECK-NEXT: blah %r3
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: jl .L{{.*}}
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; CHECK: br %r14
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entry:
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%ext = sext i32 %val to i64
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call void asm sideeffect "blah $0", "{r3}"(i64 %ext)
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%cmp = icmp slt i32 %val, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %val, i32 *%dest
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br label %exit
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exit:
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ret i32 %val
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}
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