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Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests. 

llvm-svn: 138246
This commit is contained in:
Owen Anderson 2011-08-22 17:56:58 +00:00
parent aa42847164
commit b49813206b
2 changed files with 31 additions and 1 deletions
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2
llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -2322,7 +2322,7 @@ static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Inst.addOperand(MCOperand::CreateImm(Val << 2));
Inst.addOperand(MCOperand::CreateImm(Val));
return Success;
}

30
llvm/test/MC/Disassembler/ARM/thumb1.txt
View File

@ -101,3 +101,33 @@
0x6c 0x40
#------------------------------------------------------------------------------
# LDM
#------------------------------------------------------------------------------
# CHECK: ldm r3, {r0, r1, r2, r3, r4, r5, r6, r7}
# CHECK: ldm r2!, {r1, r3, r4, r5, r7}
# CHECK: ldm r1, {r1}
0xff 0xcb
0xba 0xca
0x02 0xc9
#------------------------------------------------------------------------------
# LDR (immediate)
#------------------------------------------------------------------------------
# CHECK: ldr r1, [r5]
# CHECK: ldr r2, [r6, #32]
# CHECK: ldr r3, [r7, #124]
# CHECK: ldr r1, [sp]
# CHECK: ldr r2, [sp, #24]
# CHECK: ldr r3, [sp, #1020]
0x29 0x68
0x32 0x6a
0xfb 0x6f
0x00 0x99
0x06 0x9a
0xff 0x9b