forked from OSchip/llvm-project
[X86] Use SIMD_EXC to remove some let statements in tablegen. NFCI
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@ -1795,18 +1795,16 @@ multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
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SDNode OpNode, ValueType VT,
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PatFrag ld_frag, string asm,
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X86FoldableSchedWrite sched> {
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let Uses = [MXCSR], mayRaiseFPException = 1 in {
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let isCommutable = 1 in
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def rr : SIi8<0xC2, MRMSrcReg,
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(outs RC:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc), asm,
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[(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, timm:$cc))]>,
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Sched<[sched]>;
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Sched<[sched]>, SIMD_EXC;
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def rm : SIi8<0xC2, MRMSrcMem,
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(outs RC:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc), asm,
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[(set RC:$dst, (OpNode (VT RC:$src1),
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(ld_frag addr:$src2), timm:$cc))]>,
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Sched<[sched.Folded, sched.ReadAfterFold]>;
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}
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Sched<[sched.Folded, sched.ReadAfterFold]>, SIMD_EXC;
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}
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let isCodeGenOnly = 1 in {
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@ -1835,19 +1833,17 @@ let isCodeGenOnly = 1 in {
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multiclass sse12_cmp_scalar_int<Operand memop,
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Intrinsic Int, string asm, X86FoldableSchedWrite sched,
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PatFrags mem_frags> {
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let Uses = [MXCSR], mayRaiseFPException = 1 in {
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def rr_Int : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, u8imm:$cc), asm,
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[(set VR128:$dst, (Int VR128:$src1,
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VR128:$src2, timm:$cc))]>,
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Sched<[sched]>;
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let mayLoad = 1 in
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Sched<[sched]>, SIMD_EXC;
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let mayLoad = 1 in
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def rm_Int : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, memop:$src2, u8imm:$cc), asm,
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[(set VR128:$dst, (Int VR128:$src1,
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(mem_frags addr:$src2), timm:$cc))]>,
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Sched<[sched.Folded, sched.ReadAfterFold]>;
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}
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Sched<[sched.Folded, sched.ReadAfterFold]>, SIMD_EXC;
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}
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// Aliases to match intrinsics which expect XMM operand(s).
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@ -1878,18 +1874,17 @@ multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
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ValueType vt, X86MemOperand x86memop,
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PatFrag ld_frag, string OpcodeStr, Domain d,
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X86FoldableSchedWrite sched = WriteFComX> {
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let hasSideEffects = 0, Uses = [MXCSR], mayRaiseFPException = 1,
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ExeDomain = d in {
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let ExeDomain = d in {
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def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
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[(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))]>,
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Sched<[sched]>;
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let mayLoad = 1 in
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Sched<[sched]>, SIMD_EXC;
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let mayLoad = 1 in
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def rm: SI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
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[(set EFLAGS, (OpNode (vt RC:$src1),
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(ld_frag addr:$src2)))]>,
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Sched<[sched.Folded, sched.ReadAfterFold]>;
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Sched<[sched.Folded, sched.ReadAfterFold]>, SIMD_EXC;
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}
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}
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@ -1899,17 +1894,17 @@ multiclass sse12_ord_cmp_int<bits<8> opc, RegisterClass RC, SDNode OpNode,
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PatFrags mem_frags, string OpcodeStr,
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Domain d,
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X86FoldableSchedWrite sched = WriteFComX> {
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let Uses = [MXCSR], mayRaiseFPException = 1, ExeDomain = d in {
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let ExeDomain = d in {
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def rr_Int: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
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[(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))]>,
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Sched<[sched]>;
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Sched<[sched]>, SIMD_EXC;
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let mayLoad = 1 in
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def rm_Int: SI<opc, MRMSrcMem, (outs), (ins RC:$src1, memop:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
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[(set EFLAGS, (OpNode (vt RC:$src1),
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(mem_frags addr:$src2)))]>,
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Sched<[sched.Folded, sched.ReadAfterFold]>;
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Sched<[sched.Folded, sched.ReadAfterFold]>, SIMD_EXC;
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}
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}
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@ -1961,18 +1956,16 @@ multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
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ValueType VT, string asm,
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X86FoldableSchedWrite sched,
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Domain d, PatFrag ld_frag> {
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let Uses = [MXCSR], mayRaiseFPException = 1 in {
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let isCommutable = 1 in
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def rri : PIi8<0xC2, MRMSrcReg,
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(outs RC:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc), asm,
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[(set RC:$dst, (VT (X86any_cmpp RC:$src1, RC:$src2, timm:$cc)))], d>,
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Sched<[sched]>;
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Sched<[sched]>, SIMD_EXC;
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def rmi : PIi8<0xC2, MRMSrcMem,
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(outs RC:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc), asm,
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[(set RC:$dst,
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(VT (X86any_cmpp RC:$src1, (ld_frag addr:$src2), timm:$cc)))], d>,
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Sched<[sched.Folded, sched.ReadAfterFold]>;
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}
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Sched<[sched.Folded, sched.ReadAfterFold]>, SIMD_EXC;
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}
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defm VCMPPS : sse12_cmp_packed<VR128, f128mem, v4f32,
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