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[RISCV] Change function alignment to 4 bytes, and 2 bytes for RVC 

Summary:

According RISC-V ELF psABI specification, base RV32 and RV64 ISAs only
allow 32-bit instruction alignment, but instruction allow to be aligned
to 16-bit boundaries for C-extension.

So we just align to 4 bytes and 2 bytes for C-extension is enough.

Reviewers: asb, apazos

Differential Revision: https://reviews.llvm.org/D45560

Patch by Kito Cheng.

llvm-svn: 329899
This commit is contained in:
Shiva Chen 2018-04-12 11:30:59 +00:00
parent 69e0e8e3d4
commit b48b027d05
2 changed files with 16 additions and 2 deletions
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5
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View File

@ -142,8 +142,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setBooleanContents(ZeroOrOneBooleanContent);
// Function alignments (log2).
setMinFunctionAlignment(3);
setPrefFunctionAlignment(3);
unsigned FunctionAlignment = Subtarget.hasStdExtC() ? 1 : 2;
setMinFunctionAlignment(FunctionAlignment);
setPrefFunctionAlignment(FunctionAlignment);
// Effectively disable jump table generation.
setMinimumJumpTableEntries(INT_MAX);

13
llvm/test/CodeGen/RISCV/align.ll Normal file
View File

@ -0,0 +1,13 @@
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I
; RUN: llc -mtriple=riscv32 -mattr=+c -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32C
define void @foo() {
;RV32I: .p2align 2
;RV32I: foo:
;RV32C: .p2align 1
;RV32C: foo:
entry:
ret void
}