forked from OSchip/llvm-project
parent
7d13eae254
commit
b484f7c55e
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@ -16,6 +16,12 @@
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include "IA64InstrFormats.td"
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include "IA64InstrFormats.td"
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def u6imm : Operand<i8>;
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def u6imm : Operand<i8>;
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def s8imm : Operand<i8> {
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let PrintMethod = "printS8ImmOperand";
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}
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def s14imm : Operand<i16> {
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let PrintMethod = "printS14ImmOperand";
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}
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def s16imm : Operand<i16>;
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def s16imm : Operand<i16>;
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def s21imm : Operand<i32> {
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def s21imm : Operand<i32> {
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let PrintMethod = "printS21ImmOperand";
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let PrintMethod = "printS21ImmOperand";
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@ -107,8 +113,12 @@ def SHLI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s21imm:$imm),
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"shl $dst = $src1, $imm;;">; // FIXME: 6 immediate bits, not 21
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"shl $dst = $src1, $imm;;">; // FIXME: 6 immediate bits, not 21
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def SHRU : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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def SHRU : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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"shr.u $dst = $src1, $src2;;">;
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"shr.u $dst = $src1, $src2;;">;
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def SHRUI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s21imm:$imm),
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"shr.u $dst = $src1, $imm;;">;
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def SHRS : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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def SHRS : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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"shr $dst = $src1, $src2;;">;
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"shr $dst = $src1, $src2;;">;
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def SHRSI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s21imm:$imm),
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"shr $dst = $src1, $imm;;">;
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def DEPZ : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2), "dep.z $dst = $src1, $imm1, $imm2;;">;
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def DEPZ : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2), "dep.z $dst = $src1, $imm1, $imm2;;">;
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@ -177,6 +187,8 @@ def BCMPEQ : AForm<0x03, 0x0b, (ops PR:$dst1, PR:$dst2, GR:$src1, GR:$src2),
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def ADD : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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def ADD : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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"add $dst = $src1, $src2;;">;
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"add $dst = $src1, $src2;;">;
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def ADDIMM14 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm),
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"adds $dst = $imm, $src1;;">;
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def ADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s21imm:$imm),
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def ADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s21imm:$imm),
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"add $dst = $imm, $src1;;">;
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"add $dst = $imm, $src1;;">;
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@ -194,6 +206,8 @@ def TPCMPIMM8NE : AForm<0x03, 0x0b,
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def SUB : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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def SUB : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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"sub $dst = $src1, $src2;;">;
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"sub $dst = $src1, $src2;;">;
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def SUBIMM8 : AForm<0x03, 0x0b, (ops GR:$dst, s8imm:$imm, GR:$src2),
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"sub $dst = $imm, $src2;;">;
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def ST1 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
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def ST1 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
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"st1 [$dstPtr] = $value;;">;
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"st1 [$dstPtr] = $value;;">;
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