forked from OSchip/llvm-project
Hexagon V60/HVX DFA scheduler support
Extended DFA tablegen to: - added "-debug-only dfa-emitter" support to llvm-tblgen - defined CVI_PIPE* resources for the V60 vector coprocessor - allow specification of multiple required resources - supports ANDs of ORs - e.g. [SLOT2, SLOT3], [CVI_MPY0, CVI_MPY1] means: (SLOT2 OR SLOT3) AND (CVI_MPY0 OR CVI_MPY1) - added support for combo resources - allows specifying ORs of ANDs - e.g. [CVI_XLSHF, CVI_MPY01] means: (CVI_XLANE AND CVI_SHIFT) OR (CVI_MPY0 AND CVI_MPY1) - increased DFA input size from 32-bit to 64-bit - allows for a maximum of 4 AND'ed terms of 16 resources - supported expressions now include: expression => term [AND term] [AND term] [AND term] term => resource [OR resource]* resource => one_resource | combo_resource combo_resource => (one_resource [AND one_resource]*) Author: Dan Palermo <dpalermo@codeaurora.org> kparzysz: Verified AMDGPU codegen to be unchanged on all llc tests, except those dealing with instruction encodings. Reapply the previous patch, this time without circular dependencies. llvm-svn: 253793
This commit is contained in:
parent
a5ea5289ff
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llvm
include/llvm
lib
utils/TableGen
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@ -27,6 +27,7 @@
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#define LLVM_CODEGEN_DFAPACKETIZER_H
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/CodeGen/DFAPacketizerDefs.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include <map>
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@ -42,20 +43,21 @@ class SUnit;
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class DFAPacketizer {
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private:
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typedef std::pair<unsigned, unsigned> UnsignPair;
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typedef std::pair<unsigned, DFAInput> UnsignPair;
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const InstrItineraryData *InstrItins;
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int CurrentState;
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const int (*DFAStateInputTable)[2];
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const DFAStateInput (*DFAStateInputTable)[2];
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const unsigned *DFAStateEntryTable;
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// CachedTable is a map from <FromState, Input> to ToState.
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DenseMap<UnsignPair, unsigned> CachedTable;
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// ReadTable - Read the DFA transition table and update CachedTable.
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void ReadTable(unsigned int state);
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void ReadTable(unsigned state);
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public:
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DFAPacketizer(const InstrItineraryData *I, const int (*SIT)[2],
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DFAPacketizer(const InstrItineraryData *I, const DFAStateInput (*SIT)[2],
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const unsigned *SET);
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// Reset the current state to make all resources available.
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@ -63,6 +65,14 @@ public:
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CurrentState = 0;
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}
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// getInsnInput - Return the DFAInput for an instruction class.
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DFAInput getInsnInput(unsigned InsnClass);
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// getInsnInput - Return the DFAInput for an instruction class input vector.
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static DFAInput getInsnInput(const std::vector<unsigned> &InsnClass) {
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return getDFAInsnInput(InsnClass);
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}
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// canReserveResources - Check if the resources occupied by a MCInstrDesc
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// are available in the current state.
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bool canReserveResources(const llvm::MCInstrDesc *MID);
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@ -0,0 +1,63 @@
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//=- llvm/CodeGen/DFAPacketizerDefs.h - DFA Packetizer for VLIW ---*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// Common definitions used by TableGen and the DFAPacketizer in CodeGen.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_DFAPACKETIZERDEFS_H
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#define LLVM_CODEGEN_DFAPACKETIZERDEFS_H
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#include <vector>
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namespace llvm {
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// DFA_MAX_RESTERMS * DFA_MAX_RESOURCES must fit within sizeof DFAInput.
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// This is verified in DFAPacketizer.cpp:DFAPacketizer::DFAPacketizer.
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//
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// e.g. terms x resource bit combinations that fit in uint32_t:
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// 4 terms x 8 bits = 32 bits
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// 3 terms x 10 bits = 30 bits
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// 2 terms x 16 bits = 32 bits
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//
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// e.g. terms x resource bit combinations that fit in uint64_t:
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// 8 terms x 8 bits = 64 bits
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// 7 terms x 9 bits = 63 bits
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// 6 terms x 10 bits = 60 bits
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// 5 terms x 12 bits = 60 bits
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// 4 terms x 16 bits = 64 bits <--- current
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// 3 terms x 21 bits = 63 bits
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// 2 terms x 32 bits = 64 bits
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//
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#define DFA_MAX_RESTERMS 4 // The max # of AND'ed resource terms.
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#define DFA_MAX_RESOURCES 16 // The max # of resource bits in one term.
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typedef uint64_t DFAInput;
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typedef int64_t DFAStateInput;
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#define DFA_TBLTYPE "int64_t" // For generating DFAStateInputTable.
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namespace {
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DFAInput addDFAFuncUnits(DFAInput Inp, unsigned FuncUnits) {
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return (Inp << DFA_MAX_RESOURCES) | FuncUnits;
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}
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/// Return the DFAInput for an instruction class input vector.
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/// This function is used in both DFAPacketizer.cpp and in
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/// DFAPacketizerEmitter.cpp.
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DFAInput getDFAInsnInput(const std::vector<unsigned> &InsnClass) {
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DFAInput InsnInput = 0;
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assert ((InsnClass.size() <= DFA_MAX_RESTERMS) &&
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"Exceeded maximum number of DFA terms");
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for (auto U : InsnClass)
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InsnInput = addDFAFuncUnits(InsnInput, U);
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return InsnInput;
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}
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}
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}
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#endif
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@ -134,3 +134,19 @@ class ProcessorItineraries<list<FuncUnit> fu, list<Bypass> bp,
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// info. Subtargets using NoItineraries can bypass the scheduler's
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// expensive HazardRecognizer because no reservation table is needed.
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def NoItineraries : ProcessorItineraries<[], [], []>;
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//===----------------------------------------------------------------------===//
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// Combo Function Unit data - This is a map of combo function unit names to
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// the list of functional units that are included in the combination.
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//
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class ComboFuncData<FuncUnit ComboFunc, list<FuncUnit> funclist> {
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FuncUnit TheComboFunc = ComboFunc;
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list<FuncUnit> FuncList = funclist;
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}
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//===----------------------------------------------------------------------===//
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// Combo Function Units - This is a list of all combo function unit data.
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class ComboFuncUnits<list<ComboFuncData> cfd> {
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list<ComboFuncData> CFD = cfd;
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}
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@ -31,10 +31,17 @@
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#include "llvm/Target/TargetInstrInfo.h"
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using namespace llvm;
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DFAPacketizer::DFAPacketizer(const InstrItineraryData *I, const int (*SIT)[2],
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DFAPacketizer::DFAPacketizer(const InstrItineraryData *I,
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const DFAStateInput (*SIT)[2],
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const unsigned *SET):
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InstrItins(I), CurrentState(0), DFAStateInputTable(SIT),
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DFAStateEntryTable(SET) {}
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DFAStateEntryTable(SET) {
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// Make sure DFA types are large enough for the number of terms & resources.
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assert((DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) <= (8 * sizeof(DFAInput))
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&& "(DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) too big for DFAInput");
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assert((DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) <= (8 * sizeof(DFAStateInput))
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&& "(DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) too big for DFAStateInput");
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}
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//
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DFAStateInputTable[i][1];
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}
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//
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// getInsnInput - Return the DFAInput for an instruction class.
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//
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DFAInput DFAPacketizer::getInsnInput(unsigned InsnClass) {
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// Note: this logic must match that in DFAPacketizerDefs.h for input vectors.
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DFAInput InsnInput = 0;
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unsigned i = 0;
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for (const InstrStage *IS = InstrItins->beginStage(InsnClass),
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*IE = InstrItins->endStage(InsnClass); IS != IE; ++IS, ++i) {
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InsnInput = addDFAFuncUnits(InsnInput, IS->getUnits());
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assert ((i < DFA_MAX_RESTERMS) && "Exceeded maximum number of DFA inputs");
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}
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return InsnInput;
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}
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// canReserveResources - Check if the resources occupied by a MCInstrDesc
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// are available in the current state.
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bool DFAPacketizer::canReserveResources(const llvm::MCInstrDesc *MID) {
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unsigned InsnClass = MID->getSchedClass();
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const llvm::InstrStage *IS = InstrItins->beginStage(InsnClass);
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unsigned FuncUnits = IS->getUnits();
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UnsignPair StateTrans = UnsignPair(CurrentState, FuncUnits);
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DFAInput InsnInput = getInsnInput(InsnClass);
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UnsignPair StateTrans = UnsignPair(CurrentState, InsnInput);
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ReadTable(CurrentState);
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return (CachedTable.count(StateTrans) != 0);
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}
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// reserveResources - Reserve the resources occupied by a MCInstrDesc and
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// change the current state to reflect that change.
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void DFAPacketizer::reserveResources(const llvm::MCInstrDesc *MID) {
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unsigned InsnClass = MID->getSchedClass();
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const llvm::InstrStage *IS = InstrItins->beginStage(InsnClass);
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unsigned FuncUnits = IS->getUnits();
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UnsignPair StateTrans = UnsignPair(CurrentState, FuncUnits);
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DFAInput InsnInput = getInsnInput(InsnClass);
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UnsignPair StateTrans = UnsignPair(CurrentState, InsnInput);
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ReadTable(CurrentState);
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assert(CachedTable.count(StateTrans) != 0);
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CurrentState = CachedTable[StateTrans];
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@ -20,6 +20,15 @@ def CVI_XLSHF : FuncUnit;
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def CVI_MPY01 : FuncUnit;
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def CVI_ALL : FuncUnit;
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// Combined functional unit data.
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def HexagonComboFuncsV60 :
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ComboFuncUnits<[
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ComboFuncData<CVI_XLSHF , [CVI_XLANE, CVI_SHIFT]>,
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ComboFuncData<CVI_MPY01 , [CVI_MPY0, CVI_MPY1]>,
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ComboFuncData<CVI_ALL , [CVI_ST, CVI_XLANE, CVI_SHIFT,
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CVI_MPY0, CVI_MPY1, CVI_LD]>
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]>;
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// Note: When adding additional vector scheduling classes, add the
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// corresponding methods to the class HexagonInstrInfo.
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def CVI_VA : InstrItinClass;
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "dfa-emitter"
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#include "CodeGenTarget.h"
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#include "llvm/ADT/DenseSet.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/CodeGen/DFAPacketizerDefs.h"
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#include "llvm/TableGen/Record.h"
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#include "llvm/TableGen/TableGenBackend.h"
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#include "llvm/Support/Debug.h"
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#include <list>
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#include <map>
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#include <string>
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#include <queue>
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using namespace llvm;
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// To enable debugging, run llvm-tblgen with: "-debug-only dfa-emitter".
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//
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// dbgsInsnClass - When debugging, print instruction class stages.
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//
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void dbgsInsnClass(const std::vector<unsigned> &InsnClass);
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//
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// dbgsStateInfo - When debugging, print the set of state info.
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//
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void dbgsStateInfo(const std::set<unsigned> &stateInfo);
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//
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// dbgsIndent - When debugging, indent by the specified amount.
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//
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void dbgsIndent(unsigned indent);
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//
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// class DFAPacketizerEmitter: class that generates and prints out the DFA
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// for resource tracking.
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// allInsnClasses is the set of all possible resources consumed by an
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// InstrStage.
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//
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DenseSet<unsigned> allInsnClasses;
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std::vector<std::vector<unsigned>> allInsnClasses;
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RecordKeeper &Records;
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public:
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DFAPacketizerEmitter(RecordKeeper &R);
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//
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// collectAllInsnClasses: Populate allInsnClasses which is a set of units
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// collectAllFuncUnits - Construct a map of function unit names to bits.
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//
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int collectAllFuncUnits(std::vector<Record*> &ProcItinList,
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std::map<std::string, unsigned> &FUNameToBitsMap,
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int &maxResources,
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raw_ostream &OS);
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//
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// collectAllComboFuncs - Construct a map from a combo function unit bit to
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// the bits of all included functional units.
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//
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int collectAllComboFuncs(std::vector<Record*> &ComboFuncList,
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std::map<std::string, unsigned> &FUNameToBitsMap,
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std::map<unsigned, unsigned> &ComboBitToBitsMap,
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raw_ostream &OS);
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//
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// collectOneInsnClass - Populate allInsnClasses with one instruction class.
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//
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int collectOneInsnClass(const std::string &ProcName,
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std::vector<Record*> &ProcItinList,
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std::map<std::string, unsigned> &FUNameToBitsMap,
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Record *ItinData,
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raw_ostream &OS);
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//
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// collectAllInsnClasses - Populate allInsnClasses which is a set of units
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// used in each stage.
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//
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void collectAllInsnClasses(const std::string &Name,
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Record *ItinData,
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unsigned &NStages,
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raw_ostream &OS);
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int collectAllInsnClasses(const std::string &ProcName,
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std::vector<Record*> &ProcItinList,
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std::map<std::string, unsigned> &FUNameToBitsMap,
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std::vector<Record*> &ItinDataList,
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int &maxStages,
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raw_ostream &OS);
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void run(raw_ostream &OS);
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};
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@ -87,7 +135,7 @@ class State {
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const int stateNum;
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mutable bool isInitial;
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mutable std::set<unsigned> stateInfo;
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typedef std::map<unsigned, const State *> TransitionMap;
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typedef std::map<std::vector<unsigned>, const State *> TransitionMap;
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mutable TransitionMap Transitions;
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State();
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@ -97,28 +145,47 @@ class State {
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}
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//
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// canAddInsnClass - Returns true if an instruction of type InsnClass is a
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// valid transition from this state, i.e., can an instruction of type InsnClass
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// be added to the packet represented by this state.
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// canMaybeAddInsnClass - Quickly verifies if an instruction of type InsnClass
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// may be a valid transition from this state i.e., can an instruction of type
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// InsnClass be added to the packet represented by this state.
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//
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// PossibleStates is the set of valid resource states that ensue from valid
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// transitions.
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// Note that for multiple stages, this quick check does not take into account
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// any possible resource competition between the stages themselves. That is
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// enforced in AddInsnClassStages which checks the cross product of all
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// stages for resource availability (which is a more involved check).
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//
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bool canAddInsnClass(unsigned InsnClass) const;
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bool canMaybeAddInsnClass(std::vector<unsigned> &InsnClass,
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std::map<unsigned, unsigned> &ComboBitToBitsMap) const;
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//
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// AddInsnClass - Return all combinations of resource reservation
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// which are possible from this state (PossibleStates).
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//
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void AddInsnClass(unsigned InsnClass, std::set<unsigned> &PossibleStates) const;
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//
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// PossibleStates is the set of valid resource states that ensue from valid
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// transitions.
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//
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void AddInsnClass(std::vector<unsigned> &InsnClass,
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std::map<unsigned, unsigned> &ComboBitToBitsMap,
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std::set<unsigned> &PossibleStates) const;
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//
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// AddInsnClassStages - Return all combinations of resource reservation
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// resulting from the cross product of all stages for this InsnClass
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// which are possible from this state (PossibleStates).
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//
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void AddInsnClassStages(std::vector<unsigned> &InsnClass,
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std::map<unsigned, unsigned> &ComboBitToBitsMap,
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unsigned chkstage, unsigned numstages,
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unsigned prevState, unsigned origState,
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DenseSet<unsigned> &VisitedResourceStates,
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std::set<unsigned> &PossibleStates) const;
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//
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// addTransition - Add a transition from this state given the input InsnClass
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//
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void addTransition(unsigned InsnClass, const State *To) const;
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void addTransition(std::vector<unsigned> InsnClass, const State *To) const;
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//
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// hasTransition - Returns true if there is a transition from this state
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// given the input InsnClass
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//
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bool hasTransition(unsigned InsnClass) const;
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bool hasTransition(std::vector<unsigned> InsnClass) const;
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};
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} // End anonymous namespace.
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//
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// writeTable: Print out a table representing the DFA.
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//
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void writeTableAndAPI(raw_ostream &OS, const std::string &ClassName);
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void writeTableAndAPI(raw_ostream &OS, const std::string &ClassName,
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int numInsnClasses = 0,
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int maxResources = 0, int numCombos = 0, int maxStages = 0);
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};
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} // End anonymous namespace.
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// To enable debugging, run llvm-tblgen with: "-debug-only dfa-emitter".
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//
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// dbgsInsnClass - When debugging, print instruction class stages.
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//
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void dbgsInsnClass(const std::vector<unsigned> &InsnClass) {
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DEBUG(dbgs() << "InsnClass: ");
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for (unsigned i = 0; i < InsnClass.size(); ++i) {
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if (i > 0) {
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DEBUG(dbgs() << ", ");
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}
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DEBUG(dbgs() << "0x" << utohexstr(InsnClass[i]));
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}
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DFAInput InsnInput = getDFAInsnInput(InsnClass);
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DEBUG(dbgs() << " (input: 0x" << utohexstr(InsnInput) << ")");
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}
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//
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// dbgsStateInfo - When debugging, print the set of state info.
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//
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void dbgsStateInfo(const std::set<unsigned> &stateInfo) {
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DEBUG(dbgs() << "StateInfo: ");
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unsigned i = 0;
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for (std::set<unsigned>::iterator SI = stateInfo.begin();
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SI != stateInfo.end(); ++SI, ++i) {
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unsigned thisState = *SI;
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if (i > 0) {
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DEBUG(dbgs() << ", ");
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}
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DEBUG(dbgs() << "0x" << utohexstr(thisState));
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}
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}
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//
|
||||
// dbgsIndent - When debugging, indent by the specified amount.
|
||||
//
|
||||
void dbgsIndent(unsigned indent) {
|
||||
for (unsigned i = 0; i < indent; ++i) {
|
||||
DEBUG(dbgs() << " ");
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// Constructors and destructors for State and DFA
|
||||
|
@ -157,10 +266,11 @@ State::State() :
|
|||
|
||||
DFA::DFA(): currentState(nullptr) {}
|
||||
|
||||
//
|
||||
//
|
||||
// addTransition - Add a transition from this state given the input InsnClass
|
||||
//
|
||||
void State::addTransition(unsigned InsnClass, const State *To) const {
|
||||
void State::addTransition(std::vector<unsigned> InsnClass, const State *To)
|
||||
const {
|
||||
assert(!Transitions.count(InsnClass) &&
|
||||
"Cannot have multiple transitions for the same input");
|
||||
Transitions[InsnClass] = To;
|
||||
|
@ -170,7 +280,7 @@ void State::addTransition(unsigned InsnClass, const State *To) const {
|
|||
// hasTransition - Returns true if there is a transition from this state
|
||||
// given the input InsnClass
|
||||
//
|
||||
bool State::hasTransition(unsigned InsnClass) const {
|
||||
bool State::hasTransition(std::vector<unsigned> InsnClass) const {
|
||||
return Transitions.count(InsnClass) > 0;
|
||||
}
|
||||
|
||||
|
@ -178,61 +288,167 @@ bool State::hasTransition(unsigned InsnClass) const {
|
|||
// AddInsnClass - Return all combinations of resource reservation
|
||||
// which are possible from this state (PossibleStates).
|
||||
//
|
||||
void State::AddInsnClass(unsigned InsnClass,
|
||||
std::set<unsigned> &PossibleStates) const {
|
||||
// PossibleStates is the set of valid resource states that ensue from valid
|
||||
// transitions.
|
||||
//
|
||||
void State::AddInsnClass(std::vector<unsigned> &InsnClass,
|
||||
std::map<unsigned, unsigned> &ComboBitToBitsMap,
|
||||
std::set<unsigned> &PossibleStates) const {
|
||||
//
|
||||
// Iterate over all resource states in currentState.
|
||||
//
|
||||
unsigned numstages = InsnClass.size();
|
||||
assert((numstages > 0) && "InsnClass has no stages");
|
||||
|
||||
for (std::set<unsigned>::iterator SI = stateInfo.begin();
|
||||
SI != stateInfo.end(); ++SI) {
|
||||
unsigned thisState = *SI;
|
||||
|
||||
//
|
||||
// Iterate over all possible resources used in InsnClass.
|
||||
// For ex: for InsnClass = 0x11, all resources = {0x01, 0x10}.
|
||||
//
|
||||
|
||||
DenseSet<unsigned> VisitedResourceStates;
|
||||
for (unsigned int j = 0; j < sizeof(InsnClass) * 8; ++j) {
|
||||
if ((0x1 << j) & InsnClass) {
|
||||
//
|
||||
// For each possible resource used in InsnClass, generate the
|
||||
// resource state if that resource was used.
|
||||
//
|
||||
unsigned ResultingResourceState = thisState | (0x1 << j);
|
||||
|
||||
DEBUG(dbgs() << " thisState: 0x" << utohexstr(thisState) << "\n");
|
||||
AddInsnClassStages(InsnClass, ComboBitToBitsMap,
|
||||
numstages - 1, numstages,
|
||||
thisState, thisState,
|
||||
VisitedResourceStates, PossibleStates);
|
||||
}
|
||||
}
|
||||
|
||||
void State::AddInsnClassStages(std::vector<unsigned> &InsnClass,
|
||||
std::map<unsigned, unsigned> &ComboBitToBitsMap,
|
||||
unsigned chkstage, unsigned numstages,
|
||||
unsigned prevState, unsigned origState,
|
||||
DenseSet<unsigned> &VisitedResourceStates,
|
||||
std::set<unsigned> &PossibleStates) const {
|
||||
|
||||
assert((chkstage < numstages) && "AddInsnClassStages: stage out of range");
|
||||
unsigned thisStage = InsnClass[chkstage];
|
||||
|
||||
dbgsIndent((1 + numstages - chkstage) << 1);
|
||||
DEBUG(dbgs() << "AddInsnClassStages " << chkstage
|
||||
<< " (0x" << utohexstr(thisStage) << ") from ");
|
||||
dbgsInsnClass(InsnClass);
|
||||
DEBUG(dbgs() << "\n");
|
||||
|
||||
//
|
||||
// Iterate over all possible resources used in thisStage.
|
||||
// For ex: for thisStage = 0x11, all resources = {0x01, 0x10}.
|
||||
//
|
||||
for (unsigned int j = 0; j < DFA_MAX_RESOURCES; ++j) {
|
||||
unsigned resourceMask = (0x1 << j);
|
||||
if (resourceMask & thisStage) {
|
||||
unsigned combo = ComboBitToBitsMap[resourceMask];
|
||||
if (combo && ((~prevState & combo) != combo)) {
|
||||
DEBUG(dbgs() << "\tSkipped Add 0x" << utohexstr(prevState)
|
||||
<< " - combo op 0x" << utohexstr(resourceMask)
|
||||
<< " (0x" << utohexstr(combo) <<") cannot be scheduled\n");
|
||||
continue;
|
||||
}
|
||||
//
|
||||
// For each possible resource used in thisStage, generate the
|
||||
// resource state if that resource was used.
|
||||
//
|
||||
unsigned ResultingResourceState = prevState | resourceMask | combo;
|
||||
dbgsIndent((2 + numstages - chkstage) << 1);
|
||||
DEBUG(dbgs() << "0x" << utohexstr(prevState)
|
||||
<< " | 0x" << utohexstr(resourceMask));
|
||||
if (combo) {
|
||||
DEBUG(dbgs() << " | 0x" << utohexstr(combo));
|
||||
}
|
||||
DEBUG(dbgs() << " = 0x" << utohexstr(ResultingResourceState) << " ");
|
||||
|
||||
//
|
||||
// If this is the final stage for this class
|
||||
//
|
||||
if (chkstage == 0) {
|
||||
//
|
||||
// Check if the resulting resource state can be accommodated in this
|
||||
// packet.
|
||||
// We compute ResultingResourceState OR thisState.
|
||||
// If the result of the OR is different than thisState, it implies
|
||||
// We compute resource OR prevState (originally started as origState).
|
||||
// If the result of the OR is different than origState, it implies
|
||||
// that there is at least one resource that can be used to schedule
|
||||
// InsnClass in the current packet.
|
||||
// thisStage in the current packet.
|
||||
// Insert ResultingResourceState into PossibleStates only if we haven't
|
||||
// processed ResultingResourceState before.
|
||||
//
|
||||
if ((ResultingResourceState != thisState) &&
|
||||
(VisitedResourceStates.count(ResultingResourceState) == 0)) {
|
||||
VisitedResourceStates.insert(ResultingResourceState);
|
||||
PossibleStates.insert(ResultingResourceState);
|
||||
if (ResultingResourceState != prevState) {
|
||||
if (VisitedResourceStates.count(ResultingResourceState) == 0) {
|
||||
VisitedResourceStates.insert(ResultingResourceState);
|
||||
PossibleStates.insert(ResultingResourceState);
|
||||
DEBUG(dbgs() << "\tResultingResourceState: 0x"
|
||||
<< utohexstr(ResultingResourceState) << "\n");
|
||||
} else {
|
||||
DEBUG(dbgs() << "\tSkipped Add - state already seen\n");
|
||||
}
|
||||
} else {
|
||||
DEBUG(dbgs() << "\tSkipped Add - no final resources available\n");
|
||||
}
|
||||
} else {
|
||||
//
|
||||
// If the current resource can be accommodated, check the next
|
||||
// stage in InsnClass for available resources.
|
||||
//
|
||||
if (ResultingResourceState != prevState) {
|
||||
DEBUG(dbgs() << "\n");
|
||||
AddInsnClassStages(InsnClass, ComboBitToBitsMap,
|
||||
chkstage - 1, numstages,
|
||||
ResultingResourceState, origState,
|
||||
VisitedResourceStates, PossibleStates);
|
||||
} else {
|
||||
DEBUG(dbgs() << "\tSkipped Add - no resources available\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// canAddInsnClass - Quickly verifies if an instruction of type InsnClass is a
|
||||
// valid transition from this state i.e., can an instruction of type InsnClass
|
||||
// be added to the packet represented by this state.
|
||||
// canMaybeAddInsnClass - Quickly verifies if an instruction of type InsnClass
|
||||
// may be a valid transition from this state i.e., can an instruction of type
|
||||
// InsnClass be added to the packet represented by this state.
|
||||
//
|
||||
bool State::canAddInsnClass(unsigned InsnClass) const {
|
||||
// Note that this routine is performing conservative checks that can be
|
||||
// quickly executed acting as a filter before calling AddInsnClassStages.
|
||||
// Any cases allowed through here will be caught later in AddInsnClassStages
|
||||
// which performs the more expensive exact check.
|
||||
//
|
||||
bool State::canMaybeAddInsnClass(std::vector<unsigned> &InsnClass,
|
||||
std::map<unsigned, unsigned> &ComboBitToBitsMap) const {
|
||||
for (std::set<unsigned>::const_iterator SI = stateInfo.begin();
|
||||
SI != stateInfo.end(); ++SI) {
|
||||
if (~*SI & InsnClass)
|
||||
|
||||
// Check to see if all required resources are available.
|
||||
bool available = true;
|
||||
|
||||
// Inspect each stage independently.
|
||||
// note: This is a conservative check as we aren't checking for
|
||||
// possible resource competition between the stages themselves
|
||||
// The full cross product is examined later in AddInsnClass.
|
||||
for (unsigned i = 0; i < InsnClass.size(); ++i) {
|
||||
unsigned resources = *SI;
|
||||
if ((~resources & InsnClass[i]) == 0) {
|
||||
available = false;
|
||||
break;
|
||||
}
|
||||
// Make sure _all_ resources for a combo function are available.
|
||||
// note: This is a quick conservative check as it won't catch an
|
||||
// unscheduleable combo if this stage is an OR expression
|
||||
// containing a combo.
|
||||
// These cases are caught later in AddInsnClass.
|
||||
unsigned combo = ComboBitToBitsMap[InsnClass[i]];
|
||||
if (combo && ((~resources & combo) != combo)) {
|
||||
DEBUG(dbgs() << "\tSkipped canMaybeAdd 0x" << utohexstr(resources)
|
||||
<< " - combo op 0x" << utohexstr(InsnClass[i])
|
||||
<< " (0x" << utohexstr(combo) <<") cannot be scheduled\n");
|
||||
available = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (available) {
|
||||
return true;
|
||||
}
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
@ -244,7 +460,6 @@ const State &DFA::newState() {
|
|||
return *IterPair.first;
|
||||
}
|
||||
|
||||
|
||||
int State::currentStateNum = 0;
|
||||
|
||||
DFAPacketizerEmitter::DFAPacketizerEmitter(RecordKeeper &R):
|
||||
|
@ -263,57 +478,100 @@ DFAPacketizerEmitter::DFAPacketizerEmitter(RecordKeeper &R):
|
|||
// the ith state.
|
||||
//
|
||||
//
|
||||
void DFA::writeTableAndAPI(raw_ostream &OS, const std::string &TargetName) {
|
||||
static const std::string SentinelEntry = "{-1, -1}";
|
||||
DFA::StateSet::iterator SI = states.begin();
|
||||
void DFA::writeTableAndAPI(raw_ostream &OS, const std::string &TargetName,
|
||||
int numInsnClasses,
|
||||
int maxResources, int numCombos, int maxStages) {
|
||||
|
||||
unsigned numStates = states.size();
|
||||
|
||||
DEBUG(dbgs() << "-----------------------------------------------------------------------------\n");
|
||||
DEBUG(dbgs() << "writeTableAndAPI\n");
|
||||
DEBUG(dbgs() << "Total states: " << numStates << "\n");
|
||||
|
||||
OS << "namespace llvm {\n";
|
||||
|
||||
OS << "\n// Input format:\n";
|
||||
OS << "#define DFA_MAX_RESTERMS " << DFA_MAX_RESTERMS
|
||||
<< "\t// maximum AND'ed resource terms\n";
|
||||
OS << "#define DFA_MAX_RESOURCES " << DFA_MAX_RESOURCES
|
||||
<< "\t// maximum resource bits in one term\n";
|
||||
|
||||
OS << "\n// " << TargetName << "DFAStateInputTable[][2] = "
|
||||
<< "pairs of <Input, NextState> for all valid\n";
|
||||
OS << "// transitions.\n";
|
||||
OS << "// " << numStates << "\tstates\n";
|
||||
OS << "// " << numInsnClasses << "\tinstruction classes\n";
|
||||
OS << "// " << maxResources << "\tresources max\n";
|
||||
OS << "// " << numCombos << "\tcombo resources\n";
|
||||
OS << "// " << maxStages << "\tstages max\n";
|
||||
OS << "const " << DFA_TBLTYPE << " "
|
||||
<< TargetName << "DFAStateInputTable[][2] = {\n";
|
||||
|
||||
// This table provides a map to the beginning of the transitions for State s
|
||||
// in DFAStateInputTable.
|
||||
std::vector<int> StateEntry(states.size());
|
||||
|
||||
OS << "namespace llvm {\n\n";
|
||||
OS << "const int " << TargetName << "DFAStateInputTable[][2] = {\n";
|
||||
std::vector<int> StateEntry(numStates+1);
|
||||
static const std::string SentinelEntry = "{-1, -1}";
|
||||
|
||||
// Tracks the total valid transitions encountered so far. It is used
|
||||
// to construct the StateEntry table.
|
||||
int ValidTransitions = 0;
|
||||
for (unsigned i = 0; i < states.size(); ++i, ++SI) {
|
||||
DFA::StateSet::iterator SI = states.begin();
|
||||
for (unsigned i = 0; i < numStates; ++i, ++SI) {
|
||||
assert ((SI->stateNum == (int) i) && "Mismatch in state numbers");
|
||||
StateEntry[i] = ValidTransitions;
|
||||
for (State::TransitionMap::iterator
|
||||
II = SI->Transitions.begin(), IE = SI->Transitions.end();
|
||||
II != IE; ++II) {
|
||||
OS << "{" << II->first << ", "
|
||||
OS << "{0x" << utohexstr(getDFAInsnInput(II->first)) << ", "
|
||||
<< II->second->stateNum
|
||||
<< "}, ";
|
||||
<< "},\t";
|
||||
}
|
||||
ValidTransitions += SI->Transitions.size();
|
||||
|
||||
// If there are no valid transitions from this stage, we need a sentinel
|
||||
// transition.
|
||||
if (ValidTransitions == StateEntry[i]) {
|
||||
OS << SentinelEntry << ",";
|
||||
OS << SentinelEntry << ",\t";
|
||||
++ValidTransitions;
|
||||
}
|
||||
|
||||
OS << " // state " << i << ": " << StateEntry[i];
|
||||
if (StateEntry[i] != (ValidTransitions-1)) { // More than one transition.
|
||||
OS << "-" << (ValidTransitions-1);
|
||||
}
|
||||
OS << "\n";
|
||||
}
|
||||
|
||||
// Print out a sentinel entry at the end of the StateInputTable. This is
|
||||
// needed to iterate over StateInputTable in DFAPacketizer::ReadTable()
|
||||
OS << SentinelEntry << "\n";
|
||||
|
||||
OS << SentinelEntry << "\t";
|
||||
OS << " // state " << numStates << ": " << ValidTransitions;
|
||||
OS << "\n";
|
||||
|
||||
OS << "};\n\n";
|
||||
OS << "// " << TargetName << "DFAStateEntryTable[i] = "
|
||||
<< "Index of the first entry in DFAStateInputTable for\n";
|
||||
OS << "// "
|
||||
<< "the ith state.\n";
|
||||
OS << "// " << numStates << " states\n";
|
||||
OS << "const unsigned int " << TargetName << "DFAStateEntryTable[] = {\n";
|
||||
|
||||
// Multiply i by 2 since each entry in DFAStateInputTable is a set of
|
||||
// two numbers.
|
||||
for (unsigned i = 0; i < states.size(); ++i)
|
||||
unsigned lastState = 0;
|
||||
for (unsigned i = 0; i < numStates; ++i) {
|
||||
if (i && ((i % 10) == 0)) {
|
||||
lastState = i-1;
|
||||
OS << " // states " << (i-10) << ":" << lastState << "\n";
|
||||
}
|
||||
OS << StateEntry[i] << ", ";
|
||||
}
|
||||
|
||||
// Print out the index to the sentinel entry in StateInputTable
|
||||
OS << ValidTransitions << ", ";
|
||||
OS << " // states " << (lastState+1) << ":" << numStates << "\n";
|
||||
|
||||
OS << "\n};\n";
|
||||
OS << "};\n";
|
||||
OS << "} // namespace\n";
|
||||
|
||||
|
||||
|
@ -332,40 +590,123 @@ void DFA::writeTableAndAPI(raw_ostream &OS, const std::string &TargetName) {
|
|||
|
||||
|
||||
//
|
||||
// collectAllInsnClasses - Populate allInsnClasses which is a set of units
|
||||
// used in each stage.
|
||||
// collectAllFuncUnits - Construct a map of function unit names to bits.
|
||||
//
|
||||
void DFAPacketizerEmitter::collectAllInsnClasses(const std::string &Name,
|
||||
Record *ItinData,
|
||||
unsigned &NStages,
|
||||
raw_ostream &OS) {
|
||||
// Collect processor itineraries.
|
||||
std::vector<Record*> ProcItinList =
|
||||
Records.getAllDerivedDefinitions("ProcessorItineraries");
|
||||
|
||||
// If just no itinerary then don't bother.
|
||||
if (ProcItinList.size() < 2)
|
||||
return;
|
||||
std::map<std::string, unsigned> NameToBitsMap;
|
||||
int DFAPacketizerEmitter::collectAllFuncUnits(
|
||||
std::vector<Record*> &ProcItinList,
|
||||
std::map<std::string, unsigned> &FUNameToBitsMap,
|
||||
int &maxFUs,
|
||||
raw_ostream &OS) {
|
||||
DEBUG(dbgs() << "-----------------------------------------------------------------------------\n");
|
||||
DEBUG(dbgs() << "collectAllFuncUnits");
|
||||
DEBUG(dbgs() << " (" << ProcItinList.size() << " itineraries)\n");
|
||||
|
||||
int totalFUs = 0;
|
||||
// Parse functional units for all the itineraries.
|
||||
for (unsigned i = 0, N = ProcItinList.size(); i < N; ++i) {
|
||||
Record *Proc = ProcItinList[i];
|
||||
const std::string &ProcName = Proc->getName();
|
||||
std::vector<Record*> FUs = Proc->getValueAsListOfDefs("FU");
|
||||
|
||||
DEBUG(dbgs() << " FU:" << i
|
||||
<< " (" << FUs.size() << " FUs) "
|
||||
<< ProcName);
|
||||
|
||||
|
||||
// Convert macros to bits for each stage.
|
||||
for (unsigned i = 0, N = FUs.size(); i < N; ++i)
|
||||
NameToBitsMap[FUs[i]->getName()] = (unsigned) (1U << i);
|
||||
unsigned numFUs = FUs.size();
|
||||
for (unsigned j = 0; j < numFUs; ++j) {
|
||||
assert ((j < DFA_MAX_RESOURCES) &&
|
||||
"Exceeded maximum number of representable resources");
|
||||
unsigned FuncResources = (unsigned) (1U << j);
|
||||
FUNameToBitsMap[FUs[j]->getName()] = FuncResources;
|
||||
DEBUG(dbgs() << " " << FUs[j]->getName()
|
||||
<< ":0x" << utohexstr(FuncResources));
|
||||
}
|
||||
if (((int) numFUs) > maxFUs) {
|
||||
maxFUs = numFUs;
|
||||
}
|
||||
totalFUs += numFUs;
|
||||
DEBUG(dbgs() << "\n");
|
||||
}
|
||||
return totalFUs;
|
||||
}
|
||||
|
||||
//
|
||||
// collectAllComboFuncs - Construct a map from a combo function unit bit to
|
||||
// the bits of all included functional units.
|
||||
//
|
||||
int DFAPacketizerEmitter::collectAllComboFuncs(
|
||||
std::vector<Record*> &ComboFuncList,
|
||||
std::map<std::string, unsigned> &FUNameToBitsMap,
|
||||
std::map<unsigned, unsigned> &ComboBitToBitsMap,
|
||||
raw_ostream &OS) {
|
||||
DEBUG(dbgs() << "-----------------------------------------------------------------------------\n");
|
||||
DEBUG(dbgs() << "collectAllComboFuncs");
|
||||
DEBUG(dbgs() << " (" << ComboFuncList.size() << " sets)\n");
|
||||
|
||||
int numCombos = 0;
|
||||
for (unsigned i = 0, N = ComboFuncList.size(); i < N; ++i) {
|
||||
Record *Func = ComboFuncList[i];
|
||||
const std::string &ProcName = Func->getName();
|
||||
std::vector<Record*> FUs = Func->getValueAsListOfDefs("CFD");
|
||||
|
||||
DEBUG(dbgs() << " CFD:" << i
|
||||
<< " (" << FUs.size() << " combo FUs) "
|
||||
<< ProcName << "\n");
|
||||
|
||||
// Convert macros to bits for each stage.
|
||||
for (unsigned j = 0, N = FUs.size(); j < N; ++j) {
|
||||
assert ((j < DFA_MAX_RESOURCES) &&
|
||||
"Exceeded maximum number of DFA resources");
|
||||
Record *FuncData = FUs[j];
|
||||
Record *ComboFunc = FuncData->getValueAsDef("TheComboFunc");
|
||||
const std::vector<Record*> &FuncList =
|
||||
FuncData->getValueAsListOfDefs("FuncList");
|
||||
std::string ComboFuncName = ComboFunc->getName();
|
||||
unsigned ComboBit = FUNameToBitsMap[ComboFuncName];
|
||||
unsigned ComboResources = ComboBit;
|
||||
DEBUG(dbgs() << " combo: " << ComboFuncName
|
||||
<< ":0x" << utohexstr(ComboResources) << "\n");
|
||||
for (unsigned k = 0, M = FuncList.size(); k < M; ++k) {
|
||||
std::string FuncName = FuncList[k]->getName();
|
||||
unsigned FuncResources = FUNameToBitsMap[FuncName];
|
||||
DEBUG(dbgs() << " " << FuncName
|
||||
<< ":0x" << utohexstr(FuncResources) << "\n");
|
||||
ComboResources |= FuncResources;
|
||||
}
|
||||
ComboBitToBitsMap[ComboBit] = ComboResources;
|
||||
numCombos++;
|
||||
DEBUG(dbgs() << " => combo bits: " << ComboFuncName << ":0x"
|
||||
<< utohexstr(ComboBit) << " = 0x"
|
||||
<< utohexstr(ComboResources) << "\n");
|
||||
}
|
||||
}
|
||||
return numCombos;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// collectOneInsnClass - Populate allInsnClasses with one instruction class
|
||||
//
|
||||
int DFAPacketizerEmitter::collectOneInsnClass(const std::string &ProcName,
|
||||
std::vector<Record*> &ProcItinList,
|
||||
std::map<std::string, unsigned> &FUNameToBitsMap,
|
||||
Record *ItinData,
|
||||
raw_ostream &OS) {
|
||||
// Collect instruction classes.
|
||||
Record *ItinDef = ItinData->getValueAsDef("TheClass");
|
||||
|
||||
const std::vector<Record*> &StageList =
|
||||
ItinData->getValueAsListOfDefs("Stages");
|
||||
|
||||
// The number of stages.
|
||||
NStages = StageList.size();
|
||||
unsigned NStages = StageList.size();
|
||||
|
||||
// For each unit.
|
||||
unsigned UnitBitValue = 0;
|
||||
DEBUG(dbgs() << " " << ItinDef->getName()
|
||||
<< "\n");
|
||||
|
||||
std::vector<unsigned> UnitBits;
|
||||
|
||||
// Compute the bitwise or of each unit used in this stage.
|
||||
for (unsigned i = 0; i < NStages; ++i) {
|
||||
|
@ -375,18 +716,72 @@ void DFAPacketizerEmitter::collectAllInsnClasses(const std::string &Name,
|
|||
const std::vector<Record*> &UnitList =
|
||||
Stage->getValueAsListOfDefs("Units");
|
||||
|
||||
DEBUG(dbgs() << " stage:" << i
|
||||
<< " [" << UnitList.size() << " units]:");
|
||||
unsigned dbglen = 26; // cursor after stage dbgs
|
||||
|
||||
// Compute the bitwise or of each unit used in this stage.
|
||||
unsigned UnitBitValue = 0;
|
||||
for (unsigned j = 0, M = UnitList.size(); j < M; ++j) {
|
||||
// Conduct bitwise or.
|
||||
std::string UnitName = UnitList[j]->getName();
|
||||
assert(NameToBitsMap.count(UnitName));
|
||||
UnitBitValue |= NameToBitsMap[UnitName];
|
||||
DEBUG(dbgs() << " " << j << ":" << UnitName);
|
||||
dbglen += 3 + UnitName.length();
|
||||
assert(FUNameToBitsMap.count(UnitName));
|
||||
UnitBitValue |= FUNameToBitsMap[UnitName];
|
||||
}
|
||||
|
||||
if (UnitBitValue != 0)
|
||||
allInsnClasses.insert(UnitBitValue);
|
||||
UnitBits.push_back(UnitBitValue);
|
||||
|
||||
while (dbglen <= 64) { // line up bits dbgs
|
||||
dbglen += 8;
|
||||
DEBUG(dbgs() << "\t");
|
||||
}
|
||||
DEBUG(dbgs() << " (bits: 0x" << utohexstr(UnitBitValue) << ")\n");
|
||||
}
|
||||
|
||||
if (UnitBits.size() > 0)
|
||||
allInsnClasses.push_back(UnitBits);
|
||||
|
||||
DEBUG(dbgs() << " ");
|
||||
dbgsInsnClass(UnitBits);
|
||||
DEBUG(dbgs() << "\n");
|
||||
|
||||
return NStages;
|
||||
}
|
||||
|
||||
//
|
||||
// collectAllInsnClasses - Populate allInsnClasses which is a set of units
|
||||
// used in each stage.
|
||||
//
|
||||
int DFAPacketizerEmitter::collectAllInsnClasses(const std::string &ProcName,
|
||||
std::vector<Record*> &ProcItinList,
|
||||
std::map<std::string, unsigned> &FUNameToBitsMap,
|
||||
std::vector<Record*> &ItinDataList,
|
||||
int &maxStages,
|
||||
raw_ostream &OS) {
|
||||
// Collect all instruction classes.
|
||||
unsigned M = ItinDataList.size();
|
||||
|
||||
int numInsnClasses = 0;
|
||||
DEBUG(dbgs() << "-----------------------------------------------------------------------------\n"
|
||||
<< "collectAllInsnClasses "
|
||||
<< ProcName
|
||||
<< " (" << M << " classes)\n");
|
||||
|
||||
// Collect stages for each instruction class for all itinerary data
|
||||
for (unsigned j = 0; j < M; j++) {
|
||||
Record *ItinData = ItinDataList[j];
|
||||
int NStages = collectOneInsnClass(ProcName, ProcItinList,
|
||||
FUNameToBitsMap, ItinData, OS);
|
||||
if (NStages > maxStages) {
|
||||
maxStages = NStages;
|
||||
}
|
||||
numInsnClasses++;
|
||||
}
|
||||
return numInsnClasses;
|
||||
}
|
||||
|
||||
//
|
||||
// Run the worklist algorithm to generate the DFA.
|
||||
|
@ -398,16 +793,35 @@ void DFAPacketizerEmitter::run(raw_ostream &OS) {
|
|||
Records.getAllDerivedDefinitions("ProcessorItineraries");
|
||||
|
||||
//
|
||||
// Collect the instruction classes.
|
||||
// Collect the Functional units.
|
||||
//
|
||||
std::map<std::string, unsigned> FUNameToBitsMap;
|
||||
int maxResources = 0;
|
||||
collectAllFuncUnits(ProcItinList,
|
||||
FUNameToBitsMap, maxResources, OS);
|
||||
|
||||
//
|
||||
// Collect the Combo Functional units.
|
||||
//
|
||||
std::map<unsigned, unsigned> ComboBitToBitsMap;
|
||||
std::vector<Record*> ComboFuncList =
|
||||
Records.getAllDerivedDefinitions("ComboFuncUnits");
|
||||
int numCombos = collectAllComboFuncs(ComboFuncList,
|
||||
FUNameToBitsMap, ComboBitToBitsMap, OS);
|
||||
|
||||
//
|
||||
// Collect the itineraries.
|
||||
//
|
||||
int maxStages = 0;
|
||||
int numInsnClasses = 0;
|
||||
for (unsigned i = 0, N = ProcItinList.size(); i < N; i++) {
|
||||
Record *Proc = ProcItinList[i];
|
||||
|
||||
// Get processor itinerary name.
|
||||
const std::string &Name = Proc->getName();
|
||||
const std::string &ProcName = Proc->getName();
|
||||
|
||||
// Skip default.
|
||||
if (Name == "NoItineraries")
|
||||
if (ProcName == "NoItineraries")
|
||||
continue;
|
||||
|
||||
// Sanity check for at least one instruction itinerary class.
|
||||
|
@ -419,15 +833,11 @@ void DFAPacketizerEmitter::run(raw_ostream &OS) {
|
|||
// Get itinerary data list.
|
||||
std::vector<Record*> ItinDataList = Proc->getValueAsListOfDefs("IID");
|
||||
|
||||
// Collect instruction classes for all itinerary data.
|
||||
for (unsigned j = 0, M = ItinDataList.size(); j < M; j++) {
|
||||
Record *ItinData = ItinDataList[j];
|
||||
unsigned NStages;
|
||||
collectAllInsnClasses(Name, ItinData, NStages, OS);
|
||||
}
|
||||
// Collect all instruction classes
|
||||
numInsnClasses += collectAllInsnClasses(ProcName, ProcItinList,
|
||||
FUNameToBitsMap, ItinDataList, maxStages, OS);
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// Run a worklist algorithm to generate the DFA.
|
||||
//
|
||||
|
@ -436,6 +846,7 @@ void DFAPacketizerEmitter::run(raw_ostream &OS) {
|
|||
Initial->isInitial = true;
|
||||
Initial->stateInfo.insert(0x0);
|
||||
SmallVector<const State*, 32> WorkList;
|
||||
// std::queue<State*> WorkList;
|
||||
std::map<std::set<unsigned>, const State*> Visited;
|
||||
|
||||
WorkList.push_back(Initial);
|
||||
|
@ -459,9 +870,15 @@ void DFAPacketizerEmitter::run(raw_ostream &OS) {
|
|||
//
|
||||
while (!WorkList.empty()) {
|
||||
const State *current = WorkList.pop_back_val();
|
||||
for (DenseSet<unsigned>::iterator CI = allInsnClasses.begin(),
|
||||
CE = allInsnClasses.end(); CI != CE; ++CI) {
|
||||
unsigned InsnClass = *CI;
|
||||
DEBUG(dbgs() << "---------------------\n");
|
||||
DEBUG(dbgs() << "Processing state: " << current->stateNum << " - ");
|
||||
dbgsStateInfo(current->stateInfo);
|
||||
DEBUG(dbgs() << "\n");
|
||||
for (unsigned i = 0; i < allInsnClasses.size(); i++) {
|
||||
std::vector<unsigned> InsnClass = allInsnClasses[i];
|
||||
DEBUG(dbgs() << i << " ");
|
||||
dbgsInsnClass(InsnClass);
|
||||
DEBUG(dbgs() << "\n");
|
||||
|
||||
std::set<unsigned> NewStateResources;
|
||||
//
|
||||
|
@ -469,32 +886,47 @@ void DFAPacketizerEmitter::run(raw_ostream &OS) {
|
|||
// and the state can accommodate this InsnClass, create a transition.
|
||||
//
|
||||
if (!current->hasTransition(InsnClass) &&
|
||||
current->canAddInsnClass(InsnClass)) {
|
||||
const State *NewState;
|
||||
current->AddInsnClass(InsnClass, NewStateResources);
|
||||
assert(!NewStateResources.empty() && "New states must be generated");
|
||||
current->canMaybeAddInsnClass(InsnClass, ComboBitToBitsMap)) {
|
||||
const State *NewState = NULL;
|
||||
current->AddInsnClass(InsnClass, ComboBitToBitsMap, NewStateResources);
|
||||
if (NewStateResources.size() == 0) {
|
||||
DEBUG(dbgs() << " Skipped - no new states generated\n");
|
||||
continue;
|
||||
}
|
||||
|
||||
DEBUG(dbgs() << "\t");
|
||||
dbgsStateInfo(NewStateResources);
|
||||
DEBUG(dbgs() << "\n");
|
||||
|
||||
//
|
||||
// If we have seen this state before, then do not create a new state.
|
||||
//
|
||||
//
|
||||
auto VI = Visited.find(NewStateResources);
|
||||
if (VI != Visited.end())
|
||||
if (VI != Visited.end()) {
|
||||
NewState = VI->second;
|
||||
else {
|
||||
DEBUG(dbgs() << "\tFound existing state: "
|
||||
<< NewState->stateNum << " - ");
|
||||
dbgsStateInfo(NewState->stateInfo);
|
||||
DEBUG(dbgs() << "\n");
|
||||
} else {
|
||||
NewState = &D.newState();
|
||||
NewState->stateInfo = NewStateResources;
|
||||
Visited[NewStateResources] = NewState;
|
||||
WorkList.push_back(NewState);
|
||||
DEBUG(dbgs() << "\tAccepted new state: "
|
||||
<< NewState->stateNum << " - ");
|
||||
dbgsStateInfo(NewState->stateInfo);
|
||||
DEBUG(dbgs() << "\n");
|
||||
}
|
||||
|
||||
|
||||
current->addTransition(InsnClass, NewState);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Print out the table.
|
||||
D.writeTableAndAPI(OS, TargetName);
|
||||
D.writeTableAndAPI(OS, TargetName,
|
||||
numInsnClasses, maxResources, numCombos, maxStages);
|
||||
}
|
||||
|
||||
namespace llvm {
|
||||
|
|
Loading…
Reference in New Issue