forked from OSchip/llvm-project
ARM: One more fix for swifterror CSR set
We use a differently ordered CSR set if the frame pointer is pushed. Add a matching ..._SwiftError version. llvm-svn: 314128
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@ -93,9 +93,13 @@ ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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}
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if (STI.getTargetLowering()->supportSwiftError() &&
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F->getAttributes().hasAttrSomewhere(Attribute::SwiftError))
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return STI.isTargetDarwin() ? CSR_iOS_SwiftError_SaveList
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: CSR_AAPCS_SwiftError_SaveList;
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F->getAttributes().hasAttrSomewhere(Attribute::SwiftError)) {
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if (STI.isTargetDarwin())
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return CSR_iOS_SwiftError_SaveList;
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return UseSplitPush ? CSR_AAPCS_SplitPush_SwiftError_SaveList :
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CSR_AAPCS_SwiftError_SaveList;
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}
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if (STI.isTargetDarwin() && F->getCallingConv() == CallingConv::CXX_FAST_TLS)
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return MF->getInfo<ARMFunctionInfo>()->isSplitCSR()
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@ -258,6 +258,10 @@ def CSR_AAPCS_SplitPush : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
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R11, R10, R9, R8,
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(sequence "D%u", 15, 8))>;
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// R8 is used to pass swifterror, remove it from CSR.
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def CSR_AAPCS_SplitPush_SwiftError : CalleeSavedRegs<(sub CSR_AAPCS_SplitPush,
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R8)>;
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// Constructors and destructors return 'this' in the ARM C++ ABI; since 'this'
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// and the pointer return value are both passed in R0 in these cases, this can
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// be partially modelled by treating R0 as a callee-saved register
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