forked from OSchip/llvm-project
[mips] Add synci instruction.
Patch by Amaury Pouly Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6421 llvm-svn: 222899
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@ -252,6 +252,11 @@ static DecodeStatus DecodeCacheOp(MCInst &Inst,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeSyncI(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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@ -1065,6 +1070,21 @@ static DecodeStatus DecodeCacheOp(MCInst &Inst,
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeSyncI(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder) {
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int Offset = SignExtend32<16>(Insn & 0xffff);
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unsigned Base = fieldFromInstruction(Insn, 21, 5);
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Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
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Inst.addOperand(MCOperand::CreateReg(Base));
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Inst.addOperand(MCOperand::CreateImm(Offset));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
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@ -411,6 +411,20 @@ class SYNC_FM : StdArch {
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let Inst{5-0} = 0xf;
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}
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class SYNCI_FM : StdArch {
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// Produced by the mem_simm16 address as reg << 16 | imm (see getMemEncoding).
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bits<21> addr;
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bits<5> rs = addr{20-16};
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bits<16> offset = addr{15-0};
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bits<32> Inst;
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let Inst{31-26} = 0b000001;
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let Inst{25-21} = rs;
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let Inst{20-16} = 0b11111;
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let Inst{15-0} = offset;
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}
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class MULT_FM<bits<6> op, bits<6> funct> : StdArch {
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bits<5> rs;
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bits<5> rt;
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@ -425,7 +425,14 @@ def MipsMemSimm11AsmOperand : AsmOperandClass {
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let RenderMethod = "addMemOperands";
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let ParserMethod = "parseMemOperand";
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let PredicateMethod = "isMemWithSimmOffset<11>";
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//let DiagnosticType = "Simm11";
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}
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def MipsMemSimm16AsmOperand : AsmOperandClass {
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let Name = "MemOffsetSimm16";
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let SuperClasses = [MipsMemAsmOperand];
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let RenderMethod = "addMemOperands";
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let ParserMethod = "parseMemOperand";
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let PredicateMethod = "isMemWithSimmOffset<16>";
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}
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def MipsInvertedImmoperand : AsmOperandClass {
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@ -470,6 +477,12 @@ def mem_simm11 : mem_generic {
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let ParserMatchClass = MipsMemSimm11AsmOperand;
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}
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def mem_simm16 : mem_generic {
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let MIOperandInfo = (ops ptr_rc, simm16);
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let EncoderMethod = "getMemEncoding";
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let ParserMatchClass = MipsMemSimm16AsmOperand;
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}
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def mem_ea : Operand<iPTR> {
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let PrintMethod = "printMemOperandEA";
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let MIOperandInfo = (ops ptr_rc, simm16);
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@ -860,6 +873,13 @@ class SYNC_FT<string opstr> :
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InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
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NoItinerary, FrmOther, opstr>;
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class SYNCI_FT<string opstr> :
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InstSE<(outs), (ins mem_simm16:$addr), !strconcat(opstr, "\t$addr"), [],
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NoItinerary, FrmOther, opstr> {
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let hasSideEffects = 1;
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let DecoderMethod = "DecodeSyncI";
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}
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let hasSideEffects = 1 in
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class TEQ_FT<string opstr, RegisterOperand RO> :
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InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
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@ -1209,6 +1229,7 @@ let DecoderNamespace = "COP3_" in {
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}
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def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32;
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def SYNCI : MMRel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2;
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def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>, ISA_MIPS2;
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def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>, ISA_MIPS2;
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@ -448,3 +448,6 @@
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# CHECK: xori $9, $6, 17767
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0x38 0xc9 0x45 0x67
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# CHECK: synci -6137($fp)
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0x07 0xdf 0xe8 0x07
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@ -448,3 +448,6 @@
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# CHECK: xori $9, $6, 17767
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0x67 0x45 0xc9 0x38
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# CHECK: synci 7500($19)
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0x4c 0x1d 0x7f 0x06
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@ -293,7 +293,6 @@
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swe $24,94($k0)
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swle $v1,-209($gp)
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swre $k0,-202($s2)
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synci 20023($s0)
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tlbginv
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tlbginvf
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tlbgp
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@ -233,3 +233,4 @@
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trunc.w.s $f28,$f30
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wsbh $k1,$9
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xor $s2,$a0,$s8
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synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e]
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@ -297,7 +297,6 @@
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swe $24,94($k0)
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swle $v1,-209($gp)
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swre $k0,-202($s2)
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synci 20023($s0)
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tlbginv
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tlbginvf
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tlbgp
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