forked from OSchip/llvm-project
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eb35a7b797
commit
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@ -4732,8 +4732,7 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
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// fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
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if (N1.getOpcode() == ISD::TRUNCATE &&
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N1.getOperand(0).getOpcode() == ISD::AND) {
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SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode());
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if (NewOp1.getNode())
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if (SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode()))
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return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, NewOp1);
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}
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@ -4742,15 +4741,12 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
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if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
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return SDValue(N, 0);
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if (N1C && !N1C->isOpaque()) {
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SDValue NewSRL = visitShiftByConstant(N, N1C);
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if (NewSRL.getNode())
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if (N1C && !N1C->isOpaque())
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if (SDValue NewSRL = visitShiftByConstant(N, N1C))
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return NewSRL;
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}
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// Attempt to convert a srl of a load into a narrower zero-extending load.
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SDValue NarrowLoad = ReduceLoadWidth(N);
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if (NarrowLoad.getNode())
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if (SDValue NarrowLoad = ReduceLoadWidth(N))
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return NarrowLoad;
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// Here is a common situation. We want to optimize:
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@ -5511,8 +5507,7 @@ SDValue DAGCombiner::visitVSELECT(SDNode *N) {
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if (N1.getOpcode() == ISD::CONCAT_VECTORS &&
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N2.getOpcode() == ISD::CONCAT_VECTORS &&
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ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) {
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SDValue CV = ConvertSelectToConcatVector(N, DAG);
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if (CV.getNode())
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if (SDValue CV = ConvertSelectToConcatVector(N, DAG))
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return CV;
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}
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@ -6363,8 +6358,7 @@ SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
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// fold (aext (truncate (load x))) -> (aext (smaller load x))
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// fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
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if (N0.getOpcode() == ISD::TRUNCATE) {
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SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
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if (NarrowLoad.getNode()) {
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if (SDValue NarrowLoad = ReduceLoadWidth(N0.getNode())) {
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SDNode* oye = N0.getNode()->getOperand(0).getNode();
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if (NarrowLoad.getNode() != N0.getNode()) {
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CombineTo(N0.getNode(), NarrowLoad);
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@ -7984,8 +7978,7 @@ SDValue DAGCombiner::visitFADD(SDNode *N) {
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} // enable-unsafe-fp-math
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// FADD -> FMA combines:
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SDValue Fused = visitFADDForFMACombine(N);
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if (Fused) {
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if (SDValue Fused = visitFADDForFMACombine(N)) {
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AddToWorklist(Fused.getNode());
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return Fused;
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}
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@ -8049,8 +8042,7 @@ SDValue DAGCombiner::visitFSUB(SDNode *N) {
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}
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// FSUB -> FMA combines:
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SDValue Fused = visitFSUBForFMACombine(N);
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if (Fused) {
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if (SDValue Fused = visitFSUBForFMACombine(N)) {
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AddToWorklist(Fused.getNode());
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return Fused;
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}
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@ -9037,8 +9029,7 @@ SDValue DAGCombiner::visitBRCOND(SDNode *N) {
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SDValue Op1 = TheXor->getOperand(1);
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if (Op0.getOpcode() == Op1.getOpcode()) {
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// Avoid missing important xor optimizations.
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SDValue Tmp = visitXOR(TheXor);
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if (Tmp.getNode()) {
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if (SDValue Tmp = visitXOR(TheXor)) {
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if (Tmp.getNode() != TheXor) {
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DEBUG(dbgs() << "\nReplacing.8 ";
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TheXor->dump(&DAG);
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@ -11319,8 +11310,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
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// Try transforming a pair floating point load / store ops to integer
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// load / store ops.
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SDValue NewST = TransformFPLoadStorePair(N);
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if (NewST.getNode())
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if (SDValue NewST = TransformFPLoadStorePair(N))
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return NewST;
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bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA
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