forked from OSchip/llvm-project
[ARM] Allow SP in rGPR, starting from ARMv8
Summary: This patch handles assembly and disassembly, but not codegen, as of yet. Additionally, it fixes a bug whereby SP and PC as shifted-reg operands were treated as predictable in ARMv7 Thumb; and it enables the tests for invalid and unpredictable instructions to run on both ARMv7 and ARMv8. Reviewers: jmolloy, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D14141 llvm-svn: 251516
This commit is contained in:
Artyom Skrobov
parent
039b10423a
commit
b43981076a
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@ -343,6 +343,7 @@ public:
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Match_RequiresNotITBlock,
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Match_RequiresV6,
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Match_RequiresThumb2,
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Match_RequiresV8,
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#define GET_OPERAND_DIAGNOSTIC_TYPES
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#include "ARMGenAsmMatcher.inc"
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@ -8529,18 +8530,29 @@ unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
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if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
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inITBlock())
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return Match_RequiresNotITBlock;
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} else if (isThumbOne()) {
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// Some high-register supporting Thumb1 encodings only allow both registers
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// to be from r0-r7 when in Thumb2.
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if (Opc == ARM::tADDhirr && !hasV6MOps() &&
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isARMLowRegister(Inst.getOperand(1).getReg()) &&
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isARMLowRegister(Inst.getOperand(2).getReg()))
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return Match_RequiresThumb2;
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// Others only require ARMv6 or later.
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else if (Opc == ARM::tMOVr && !hasV6Ops() &&
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isARMLowRegister(Inst.getOperand(0).getReg()) &&
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isARMLowRegister(Inst.getOperand(1).getReg()))
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return Match_RequiresV6;
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}
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// Some high-register supporting Thumb1 encodings only allow both registers
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// to be from r0-r7 when in Thumb2.
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else if (Opc == ARM::tADDhirr && isThumbOne() && !hasV6MOps() &&
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isARMLowRegister(Inst.getOperand(1).getReg()) &&
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isARMLowRegister(Inst.getOperand(2).getReg()))
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return Match_RequiresThumb2;
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// Others only require ARMv6 or later.
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else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
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isARMLowRegister(Inst.getOperand(0).getReg()) &&
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isARMLowRegister(Inst.getOperand(1).getReg()))
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return Match_RequiresV6;
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for (unsigned I = 0; I < MCID.NumOperands; ++I)
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if (MCID.OpInfo[I].RegClass == ARM::rGPRRegClassID) {
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// rGPRRegClass excludes PC, and also excluded SP before ARMv8
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if ((Inst.getOperand(I).getReg() == ARM::SP) && !hasV8Ops())
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return Match_RequiresV8;
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else if (Inst.getOperand(I).getReg() == ARM::PC)
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return Match_InvalidOperand;
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}
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return Match_Success;
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}
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@ -8639,6 +8651,8 @@ bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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return Error(IDLoc, "instruction variant requires ARMv6 or later");
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case Match_RequiresThumb2:
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return Error(IDLoc, "instruction variant requires Thumb2");
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case Match_RequiresV8:
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return Error(IDLoc, "instruction variant requires ARMv8 or later");
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case Match_ImmRange0_15: {
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SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
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if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
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@ -9996,6 +10010,10 @@ unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
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"expression value must be representable in 32 bits");
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}
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break;
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case MCK_rGPR:
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if (hasV8Ops() && Op.isReg() && Op.getReg() == ARM::SP)
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return Match_Success;
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break;
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case MCK_GPRPair:
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if (Op.isReg() &&
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MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg()))
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@ -966,8 +966,13 @@ static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
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static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder) {
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DecodeStatus S = MCDisassembler::Success;
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if (RegNo == 13 || RegNo == 15)
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const FeatureBitset &featureBits =
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((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
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if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
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S = MCDisassembler::SoftFail;
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Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
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return S;
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}
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@ -1127,7 +1132,7 @@ static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
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unsigned imm = fieldFromInstruction(Val, 7, 5);
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// Register-immediate
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if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
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if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
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return MCDisassembler::Fail;
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ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
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@ -3,7 +3,7 @@
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@ RUN: llvm-mc -triple thumbv8 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-V8
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@ RUN: not llvm-mc -triple thumbv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7
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@ HLT
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@ HLT (in ARMv8 only)
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hlt #0
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hlt #63
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@ CHECK-V8: hlt #0 @ encoding: [0x80,0xba]
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@ -19,12 +19,23 @@
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@ CHECK-V8: hlt #24 @ encoding: [0x98,0xba]
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@ CHECK-V7: error: instruction requires: armv8
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@ Can accept AL condition code
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@ Can accept AL condition code (in ARMv8 only)
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hltal #24
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@ CHECK-V8: hlt #24 @ encoding: [0x98,0xba]
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@ CHECK-V7: error: instruction requires: armv8
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@ DCPS{1,2,3}
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@ Can accept SP as rGPR (in ARMv8 only)
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sbc.w r6, r3, sp, asr #16
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and.w r6, r3, sp, asr #16
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and sp, r0, #0
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@ CHECK-V8: sbc.w r6, r3, sp, asr #16 @ encoding: [0x63,0xeb,0x2d,0x46]
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@ CHECK-V8: and.w r6, r3, sp, asr #16 @ encoding: [0x03,0xea,0x2d,0x46]
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@ CHECK-V8: and sp, r0, #0 @ encoding: [0x00,0xf0,0x00,0x0d]
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@ CHECK-V7: error: instruction variant requires ARMv8 or later
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@ CHECK-V7: error: instruction variant requires ARMv8 or later
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@ CHECK-V7: error: invalid operand for instruction
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@ DCPS{1,2,3} (in ARMv8 only)
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dcps1
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dcps2
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dcps3
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@ -36,7 +47,7 @@
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@ CHECK-V7: error: instruction requires: armv8
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@------------------------------------------------------------------------------
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@ DMB (v8 barriers)
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@ DMB (ARMv8-only barriers)
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@------------------------------------------------------------------------------
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dmb ishld
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dmb oshld
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@ -53,7 +64,7 @@
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@ CHECK-V7: error: invalid operand for instruction
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@------------------------------------------------------------------------------
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@ DSB (v8 barriers)
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@ DSB (ARMv8-only barriers)
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@------------------------------------------------------------------------------
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dsb ishld
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dsb oshld
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@ -70,7 +81,7 @@
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@ CHECK-V7: error: invalid operand for instruction
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@------------------------------------------------------------------------------
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@ SEVL
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@ SEVL (in ARMv8 only)
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@------------------------------------------------------------------------------
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sevl
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sevl.w
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@ -1,7 +1,7 @@
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@ RUN: not llvm-mc -triple=armv7-apple-darwin < %s 2> %t
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@ RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
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@ RUN: FileCheck --check-prefix=CHECK-ERRORS --check-prefix=CHECK-ERRORS-V7 < %t %s
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@ RUN: not llvm-mc -triple=armv8 < %s 2> %t
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@ RUN: FileCheck --check-prefix=CHECK-ERRORS-V8 < %t %s
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@ RUN: FileCheck --check-prefix=CHECK-ERRORS --check-prefix=CHECK-ERRORS-V8 < %t %s
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@ Check for various assembly diagnostic messages on invalid input.
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@ -98,22 +98,22 @@
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@ Out of range immediates for v8 HLT instruction.
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hlt #65536
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hlt #-1
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@CHECK-ERRORS-V8: error: invalid operand for instruction
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@CHECK-ERRORS-V8: hlt #65536
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@CHECK-ERRORS-V8: ^
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@CHECK-ERRORS-V8: error: invalid operand for instruction
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@CHECK-ERRORS-V8: hlt #-1
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@CHECK-ERRORS-V8: ^
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@CHECK-ERRORS: error: invalid operand for instruction
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@CHECK-ERRORS: hlt #65536
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@CHECK-ERRORS: ^
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@CHECK-ERRORS: error: invalid operand for instruction
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@CHECK-ERRORS: hlt #-1
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@CHECK-ERRORS: ^
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@ Illegal condition code for v8 HLT instruction.
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hlteq #2
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hltlt #23
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@CHECK-ERRORS-V8: error: instruction 'hlt' is not predicable, but condition code specified
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@CHECK-ERRORS-V8: hlteq #2
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@CHECK-ERRORS-V8: ^
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@CHECK-ERRORS-V8: error: instruction 'hlt' is not predicable, but condition code specified
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@CHECK-ERRORS-V8: hltlt #23
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@CHECK-ERRORS-V8: ^
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@CHECK-ERRORS: error: instruction 'hlt' is not predicable, but condition code specified
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@CHECK-ERRORS: hlteq #2
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@CHECK-ERRORS: ^
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@CHECK-ERRORS: error: instruction 'hlt' is not predicable, but condition code specified
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@CHECK-ERRORS: hltlt #23
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@CHECK-ERRORS: ^
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@ Out of range 4 and 3 bit immediates on CDP[2]
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@ -149,7 +149,8 @@
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
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@ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
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@ CHECK-ERRORS-V7: error: immediate operand must be in the range [0,15]
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@ CHECK-ERRORS-V8: error: invalid operand for instruction
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@ p10 and p11 are reserved for NEON
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mcr p10, #2, r5, c1, c1, #4
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@ -183,7 +184,8 @@
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
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@ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
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@ CHECK-ERRORS-V7: error: immediate operand must be in the range [0,15]
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@ CHECK-ERRORS-V8: error: invalid operand for instruction
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@ Shifter operand validation for PKH instructions.
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pkhbt r2, r2, r3, lsl #-1
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@ -394,12 +396,14 @@
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ldc2 p2, c8, [r1], { 256 }
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ldc2 p2, c8, [r1], { -1 }
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@ CHECK-ERRORS: error: coprocessor option must be an immediate in range [0, 255]
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@ CHECK-ERRORS: ldc2 p2, c8, [r1], { 256 }
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: coprocessor option must be an immediate in range [0, 255]
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@ CHECK-ERRORS: ldc2 p2, c8, [r1], { -1 }
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS-V7: error: coprocessor option must be an immediate in range [0, 255]
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@ CHECK-ERRORS-V7: ldc2 p2, c8, [r1], { 256 }
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@ CHECK-ERRORS-V7: ^
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@ CHECK-ERRORS-V8: error: register expected
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@ CHECK-ERRORS-V7: error: coprocessor option must be an immediate in range [0, 255]
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@ CHECK-ERRORS-V7: ldc2 p2, c8, [r1], { -1 }
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@ CHECK-ERRORS-V7: ^
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@ CHECK-ERRORS-V8: error: register expected
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@ Bad CPS instruction format.
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cps f,#1
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@ -470,14 +474,14 @@
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vrintn.f32 s8, s9
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vrintp.f64.f64 d10, d11
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vrintm.f64 d12, d13
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@ CHECK-ERRORS: error: instruction requires: FPARMv8
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@ CHECK-ERRORS: error: instruction requires: FPARMv8
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@ CHECK-ERRORS: error: instruction requires: FPARMv8
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@ CHECK-ERRORS: error: instruction requires: FPARMv8
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@ CHECK-ERRORS: error: instruction requires: FPARMv8
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@ CHECK-ERRORS: error: instruction requires: FPARMv8
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@ CHECK-ERRORS: error: instruction requires: FPARMv8
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@ CHECK-ERRORS: error: instruction requires: FPARMv8
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@ CHECK-ERRORS-V7: error: instruction requires: FPARMv8
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@ CHECK-ERRORS-V7: error: instruction requires: FPARMv8
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@ CHECK-ERRORS-V7: error: instruction requires: FPARMv8
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@ CHECK-ERRORS-V7: error: instruction requires: FPARMv8
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@ CHECK-ERRORS-V7: error: instruction requires: FPARMv8
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@ CHECK-ERRORS-V7: error: instruction requires: FPARMv8
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@ CHECK-ERRORS-V7: error: instruction requires: FPARMv8
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@ CHECK-ERRORS-V7: error: instruction requires: FPARMv8
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stm sp!, {r0, pc}^
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ldm sp!, {r0}^
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@ -6,40 +6,40 @@
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sbc.w r12, lr, r0
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sbc.w r1, r8, r9, lsr #32
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sbc.w r2, r7, pc, lsr #16
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sbc.w r2, r7, r10, lsr #16
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sbc.w r3, r6, r10, lsl #0
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sbc.w r4, r5, lr, lsl #16
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sbc.w r5, r4, r11, asr #32
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sbc.w r6, r3, sp, asr #16
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sbc.w r6, r3, r12, asr #16
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sbc.w r7, r2, r12, rrx
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sbc.w r8, r1, r0, ror #16
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@ CHECK: sbc.w r12, lr, r0 @ encoding: [0x6e,0xeb,0x00,0x0c]
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@ CHECK: sbc.w r1, r8, r9, lsr #32 @ encoding: [0x68,0xeb,0x19,0x01]
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@ CHECK: sbc.w r2, r7, pc, lsr #16 @ encoding: [0x67,0xeb,0x1f,0x42]
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@ CHECK: sbc.w r2, r7, r10, lsr #16 @ encoding: [0x67,0xeb,0x1a,0x42]
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@ CHECK: sbc.w r3, r6, r10 @ encoding: [0x66,0xeb,0x0a,0x03]
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@ CHECK: sbc.w r4, r5, lr, lsl #16 @ encoding: [0x65,0xeb,0x0e,0x44]
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@ CHECK: sbc.w r5, r4, r11, asr #32 @ encoding: [0x64,0xeb,0x2b,0x05]
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@ CHECK: sbc.w r6, r3, sp, asr #16 @ encoding: [0x63,0xeb,0x2d,0x46]
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@ CHECK: sbc.w r6, r3, r12, asr #16 @ encoding: [0x63,0xeb,0x2c,0x46]
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@ CHECK: sbc.w r7, r2, r12, rrx @ encoding: [0x62,0xeb,0x3c,0x07]
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@ CHECK: sbc.w r8, r1, r0, ror #16 @ encoding: [0x61,0xeb,0x30,0x48]
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and.w r12, lr, r0
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and.w r1, r8, r9, lsr #32
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and.w r2, r7, pc, lsr #16
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and.w r2, r7, r10, lsr #16
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and.w r3, r6, r10, lsl #0
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and.w r4, r5, lr, lsl #16
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and.w r5, r4, r11, asr #32
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and.w r6, r3, sp, asr #16
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and.w r6, r3, r12, asr #16
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and.w r7, r2, r12, rrx
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and.w r8, r1, r0, ror #16
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@ CHECK: and.w r12, lr, r0 @ encoding: [0x0e,0xea,0x00,0x0c]
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@ CHECK: and.w r1, r8, r9, lsr #32 @ encoding: [0x08,0xea,0x19,0x01]
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@ CHECK: and.w r2, r7, pc, lsr #16 @ encoding: [0x07,0xea,0x1f,0x42]
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@ CHECK: and.w r2, r7, r10, lsr #16 @ encoding: [0x07,0xea,0x1a,0x42]
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@ CHECK: and.w r3, r6, r10 @ encoding: [0x06,0xea,0x0a,0x03]
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@ CHECK: and.w r4, r5, lr, lsl #16 @ encoding: [0x05,0xea,0x0e,0x44]
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@ CHECK: and.w r5, r4, r11, asr #32 @ encoding: [0x04,0xea,0x2b,0x05]
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@ CHECK: and.w r6, r3, sp, asr #16 @ encoding: [0x03,0xea,0x2d,0x46]
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@ CHECK: and.w r6, r3, r12, asr #16 @ encoding: [0x03,0xea,0x2c,0x46]
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@ CHECK: and.w r7, r2, r12, rrx @ encoding: [0x02,0xea,0x3c,0x07]
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@ CHECK: and.w r8, r1, r0, ror #16 @ encoding: [0x01,0xea,0x30,0x48]
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@ -1,5 +1,8 @@
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@ RUN: not llvm-mc -triple=thumbv7-apple-darwin < %s 2> %t
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@ RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
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@ RUN: FileCheck --check-prefix=CHECK-ERRORS --check-prefix=CHECK-ERRORS-V7 < %t %s
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@ RUN: not llvm-mc -triple=thumbv8-apple-darwin < %s 2> %t
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@ RUN: FileCheck --check-prefix=CHECK-ERRORS --check-prefix=CHECK-ERRORS-V8 < %t %s
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@ Ill-formed IT block instructions.
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itet eq
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@ -41,7 +44,8 @@
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
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@ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
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@ CHECK-ERRORS-V7: error: immediate operand must be in the range [0,15]
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@ CHECK-ERRORS-V8: error: invalid operand for instruction
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isb #-1
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isb #16
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@ -87,7 +91,14 @@ foo2:
|
|||
@ CHECK-ERRORS: error: invalid operand for instruction
|
||||
@ CHECK-ERRORS: error: invalid operand for instruction
|
||||
|
||||
ssat r0, #1, r0, asr #32
|
||||
usat r0, #1, r0, asr #32
|
||||
ssat r0, #1, r0, asr #32
|
||||
usat r0, #1, r0, asr #32
|
||||
@ CHECK-ERRORS: error: 'asr #32' shift amount not allowed in Thumb mode
|
||||
@ CHECK-ERRORS: error: 'asr #32' shift amount not allowed in Thumb mode
|
||||
|
||||
@ PC is not valid as shifted-rGPR
|
||||
sbc.w r2, r7, pc, lsr #16
|
||||
and.w r2, r7, pc, lsr #16
|
||||
@ CHECK-ERRORS: error: invalid operand for instruction
|
||||
@ CHECK-ERRORS: error: invalid operand for instruction
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
# RUN: not llvm-mc -disassemble %s -mcpu cortex-a8 -triple thumbv7 2>&1 | FileCheck %s
|
||||
# RUN: not llvm-mc -disassemble %s -mcpu cortex-a8 -triple thumbv7 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V7
|
||||
# RUN: not llvm-mc -disassemble %s -mcpu cortex-a53 -triple thumbv8 2>&1 | FileCheck %s
|
||||
|
||||
# This file is checking Thumbv7 encodings which are globally invalid, usually due
|
||||
# to the constraints of the instructions not being met. For example invalid
|
||||
|
|
@ -359,10 +360,22 @@
|
|||
# 32-bit Thumb STM instructions cannot have a writeback register which appears
|
||||
# in the list.
|
||||
|
||||
[0xa1,0xe8,0x07,0x04]
|
||||
[0xa1 0xe8 0x07 0x04]
|
||||
# CHECK: warning: potentially undefined instruction encoding
|
||||
# CHECK-NEXT: [0xa1,0xe8,0x07,0x04]
|
||||
# CHECK-NEXT: [0xa1 0xe8 0x07 0x04]
|
||||
|
||||
[0x21,0xe9,0x07,0x04]
|
||||
[0x21 0xe9 0x07 0x04]
|
||||
# CHECK: warning: potentially undefined instruction encoding
|
||||
# CHECK-NEXT: [0x21,0xe9,0x07,0x04]
|
||||
# CHECK-NEXT: [0x21 0xe9 0x07 0x04]
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# SP is invalid as rGPR before ARMv8
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
[0x00 0xf0 0x00 0x0d]
|
||||
# CHECK-V7: warning: potentially undefined instruction encoding
|
||||
# CHECK-V7-NEXT: [0x00 0xf0 0x00 0x0d]
|
||||
|
||||
[0x63 0xeb 0x2d 0x46]
|
||||
# CHECK-V7: warning: potentially undefined instruction encoding
|
||||
# CHECK-V7-NEXT: [0x63 0xeb 0x2d 0x46]
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
# RUN: llvm-mc -disassemble -triple thumbv8 -mattr=+db -show-encoding < %s | FileCheck %s
|
||||
# RUN: llvm-mc -disassemble -triple thumbv8 -mattr=+db -show-encoding 2>%t < %s | FileCheck %s
|
||||
# RUN: FileCheck -allow-empty -check-prefix=STDERR < %t %s
|
||||
|
||||
0x80 0xba
|
||||
# CHECK: hlt #0
|
||||
|
|
@ -26,3 +27,10 @@
|
|||
# CHECK: dmb oshld
|
||||
# CHECK: dmb nshld
|
||||
# CHECK: dmb ld
|
||||
|
||||
[0x00 0xf0 0x00 0x0d]
|
||||
[0x63 0xeb 0x2d 0x46]
|
||||
# CHECK: and sp, r0, #0
|
||||
# CHECK: sbc.w r6, r3, sp, asr #16
|
||||
|
||||
# STDERR-NOT: warning
|
||||
|
|
|
|||
Loading…
Reference in New Issue