forked from OSchip/llvm-project
Expand add/sub into ADD_PARTS/SUB_PARTS instead of a non-existant libcall.
llvm-svn: 19715
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1fe9b40981
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@ -121,6 +121,8 @@ private:
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bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
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SDOperand &Lo, SDOperand &Hi);
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void ExpandAddSub(bool isAdd, SDOperand Op, SDOperand Amt,
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SDOperand &Lo, SDOperand &Hi);
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SDOperand getIntPtrConstant(uint64_t Val) {
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return DAG.getConstant(Val, TLI.getPointerTy());
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@ -753,6 +755,18 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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}
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break;
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}
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case ISD::ADD_PARTS:
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case ISD::SUB_PARTS: {
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std::vector<SDOperand> Ops;
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bool Changed = false;
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for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
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Ops.push_back(LegalizeOp(Node->getOperand(i)));
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Changed |= Ops.back() != Node->getOperand(i);
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}
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if (Changed)
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Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops);
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break;
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}
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case ISD::ADD:
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case ISD::SUB:
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case ISD::MUL:
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@ -1183,6 +1197,27 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
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return Result;
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}
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/// ExpandAddSub - Find a clever way to expand this add operation into
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/// subcomponents.
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void SelectionDAGLegalize::ExpandAddSub(bool isAdd, SDOperand LHS,SDOperand RHS,
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SDOperand &Lo, SDOperand &Hi) {
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// Expand the subcomponents.
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SDOperand LHSL, LHSH, RHSL, RHSH;
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ExpandOp(LHS, LHSL, LHSH);
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ExpandOp(RHS, RHSL, RHSH);
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// Convert this add to the appropriate ADDC pair. The low part has no carry
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// in.
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unsigned Opc = isAdd ? ISD::ADD_PARTS : ISD::SUB_PARTS;
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std::vector<SDOperand> Ops;
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Ops.push_back(LHSL);
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Ops.push_back(LHSH);
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Ops.push_back(RHSL);
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Ops.push_back(RHSH);
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Lo = DAG.getNode(Opc, LHSL.getValueType(), Ops);
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Hi = Lo.getValue(1);
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}
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/// ExpandShift - Try to find a clever way to expand this shift operation out to
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/// smaller elements. If we can't find a way that is more efficient than a
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/// libcall on this target, return false. Otherwise, return true with the
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@ -1444,8 +1479,12 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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LibCallName = "__lshrdi3";
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break;
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case ISD::ADD: LibCallName = "__adddi3"; break;
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case ISD::SUB: LibCallName = "__subdi3"; break;
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case ISD::ADD:
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ExpandAddSub(true, Node->getOperand(0), Node->getOperand(1), Lo, Hi);
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break;
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case ISD::SUB:
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ExpandAddSub(false, Node->getOperand(0), Node->getOperand(1), Lo, Hi);
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break;
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case ISD::MUL: LibCallName = "__muldi3"; break;
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case ISD::SDIV: LibCallName = "__divdi3"; break;
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case ISD::UDIV: LibCallName = "__udivdi3"; break;
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