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Add a subtarget feature 'v8' to the ARM backend. 

This allows for targeting the ARMv8 AArch32 variant.

llvm-svn: 184967
This commit is contained in:
Joey Gouly 2013-06-26 16:58:26 +00:00
parent f4ca3994b8
commit b3f550e8cd
9 changed files with 41 additions and 11 deletions
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6
llvm/lib/Target/ARM/ARM.td
View File

@ -138,6 +138,9 @@ def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
"Support ARM v7 instructions",
[HasV6T2Ops, FeaturePerfMon]>;
def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true",
"Support ARM v8 instructions",
[HasV7Ops]>;
//===----------------------------------------------------------------------===//
// ARM Processors supported.
@ -291,6 +294,9 @@ def : ProcessorModel<"swift", SwiftModel,
FeatureDB, FeatureDSPThumb2,
FeatureHasRAS]>;
// V8 Processors
def : ProcNoItin<"cortex-a53", [HasV8Ops]>;
//===----------------------------------------------------------------------===//
// Register File Description
//===----------------------------------------------------------------------===//

4
llvm/lib/Target/ARM/ARMAsmPrinter.cpp
View File

@ -749,7 +749,9 @@ void ARMAsmPrinter::emitAttributes() {
ARMBuildAttrs::Allowed);
AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
ARMBuildAttrs::Allowed);
} else if (Subtarget->hasV7Ops()) {
} else if (Subtarget->hasV8Ops())
AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v8);
else if (Subtarget->hasV7Ops()) {
AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
ARMBuildAttrs::AllowThumb32);

3
llvm/lib/Target/ARM/ARMBuildAttrs.h
View File

@ -89,7 +89,8 @@ namespace ARMBuildAttrs {
v7 = 10, // e.g. Cortex A8, Cortex M3
v6_M = 11, // e.g. Cortex M1
v6S_M = 12, // v6_M with the System extensions
v7E_M = 13 // v7_M with DSP extensions
v7E_M = 13, // v7_M with DSP extensions
v8 = 14 // v8, AArch32
};
enum CPUArchProfile { // (=7), uleb128

2
llvm/lib/Target/ARM/ARMInstrInfo.td
View File

@ -194,6 +194,8 @@ def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
AssemblerPredicate<"HasV7Ops", "armv7">;
def HasV8 : Predicate<"Subtarget->hasV8Ops()">,
AssemblerPredicate<"HasV8Ops", "armv8">;
def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
AssemblerPredicate<"FeatureVFP2", "VFP2">;

1
llvm/lib/Target/ARM/ARMSubtarget.cpp
View File

@ -77,6 +77,7 @@ void ARMSubtarget::initializeEnvironment() {
HasV6Ops = false;
HasV6T2Ops = false;
HasV7Ops = false;
HasV8Ops = false;
HasVFPv2 = false;
HasVFPv3 = false;
HasVFPv4 = false;

5
llvm/lib/Target/ARM/ARMSubtarget.h
View File

@ -37,7 +37,8 @@ protected:
/// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
ARMProcFamilyEnum ARMProcFamily;
/// HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6T2Ops, HasV7Ops -
/// HasV4TOps, HasV5TOps, HasV5TEOps,
/// HasV6Ops, HasV6T2Ops, HasV7Ops, HasV8Ops -
/// Specify whether target support specific ARM ISA variants.
bool HasV4TOps;
bool HasV5TOps;
@ -45,6 +46,7 @@ protected:
bool HasV6Ops;
bool HasV6T2Ops;
bool HasV7Ops;
bool HasV8Ops;
/// HasVFPv2, HasVFPv3, HasVFPv4, HasNEON - Specify what
/// floating point ISAs are supported.
@ -231,6 +233,7 @@ public:
bool hasV6Ops() const { return HasV6Ops; }
bool hasV6T2Ops() const { return HasV6T2Ops; }
bool hasV7Ops() const { return HasV7Ops; }
bool hasV8Ops() const { return HasV8Ops; }
bool isCortexA5() const { return ARMProcFamily == CortexA5; }
bool isCortexA8() const { return ARMProcFamily == CortexA8; }

3
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -161,6 +161,9 @@ class ARMAsmParser : public MCTargetAsmParser {
bool hasV7Ops() const {
return STI.getFeatureBits() & ARM::HasV7Ops;
}
bool hasV8Ops() const {
return STI.getFeatureBits() & ARM::HasV8Ops;
}
bool hasARM() const {
return !(STI.getFeatureBits() & ARM::FeatureNoARM);
}

5
llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
View File

@ -59,7 +59,10 @@ std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
std::string ARMArchFeature;
if (Idx) {
unsigned SubVer = TT[Idx];
if (SubVer >= '7' && SubVer <= '9') {
if (SubVer == '8') {
// FIXME: Parse v8 features
ARMArchFeature = "+v8";
} else if (SubVer == '7') {
if (Len >= Idx+2 && TT[Idx+1] == 'm') {
isThumb = true;
if (NoCPU)

23
llvm/test/CodeGen/ARM/2010-09-29-mc-asm-header-test.ll
View File

@ -1,12 +1,21 @@
; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s
; RUN: llc < %s -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=V7
; RUN: llc < %s -mtriple=armv8-linux-gnueabi | FileCheck %s --check-prefix=V8
; RUN: llc < %s -mtriple=thumbv8-linux-gnueabi | FileCheck %s --check-prefix=Vt8
; This tests that MC/asm header conversion is smooth
;
; CHECK: .syntax unified
; CHECK: .eabi_attribute 20, 1
; CHECK: .eabi_attribute 21, 1
; CHECK: .eabi_attribute 23, 3
; CHECK: .eabi_attribute 24, 1
; CHECK: .eabi_attribute 25, 1
; V7: .syntax unified
; V7: .eabi_attribute 6, 10
; V7: .eabi_attribute 20, 1
; V7: .eabi_attribute 21, 1
; V7: .eabi_attribute 23, 3
; V7: .eabi_attribute 24, 1
; V7: .eabi_attribute 25, 1
; V8: .syntax unified
; V8: .eabi_attribute 6, 14
; Vt8: .syntax unified
; Vt8: .eabi_attribute 6, 14
define i32 @f(i64 %z) {
ret i32 0