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[AArch64] Update clang CodeGen tests I missed in 4252f7773a. 

These tests invoke opt and llc even though they are in the frontend.

We now do a better job of generating commuted patterns for fma so
these tests now form fmls instead of fmla+fneg.
This commit is contained in:
Craig Topper 2020-11-23 11:08:10 -08:00
parent b4902bcd98
commit b3f1b19c9c
1 changed files with 2 additions and 4 deletions
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6
clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics-constrained.c
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@ -69,10 +69,9 @@ float16x8_t test_vfmaq_f16(float16x8_t a, float16x8_t b, float16x8_t c) {
// COMMON-LABEL: test_vfms_f16
// COMMONIR: [[SUB:%.*]] = fneg <4 x half> %b
// CHECK-ASM: fneg v{{[0-9]+}}.4h, v{{[0-9]+}}.4h
// UNCONSTRAINED: [[ADD:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[SUB]], <4 x half> %c, <4 x half> %a)
// CONSTRAINED: [[ADD:%.*]] = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> [[SUB]], <4 x half> %c, <4 x half> %a, metadata !"round.tonearest", metadata !"fpexcept.maytrap")
// CHECK-ASM: fmla v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h
// CHECK-ASM: fmls v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h
// COMMONIR: ret <4 x half> [[ADD]]
float16x4_t test_vfms_f16(float16x4_t a, float16x4_t b, float16x4_t c) {
return vfms_f16(a, b, c);
@ -80,10 +79,9 @@ float16x4_t test_vfms_f16(float16x4_t a, float16x4_t b, float16x4_t c) {
// COMMON-LABEL: test_vfmsq_f16
// COMMONIR: [[SUB:%.*]] = fneg <8 x half> %b
// CHECK-ASM: fneg v{{[0-9]+}}.8h, v{{[0-9]+}}.8h
// UNCONSTRAINED: [[ADD:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> [[SUB]], <8 x half> %c, <8 x half> %a)
// CONSTRAINED: [[ADD:%.*]] = call <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half> [[SUB]], <8 x half> %c, <8 x half> %a, metadata !"round.tonearest", metadata !"fpexcept.maytrap")
// CHECK-ASM: fmla v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h
// CHECK-ASM: fmls v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h
// COMMONIR: ret <8 x half> [[ADD]]
float16x8_t test_vfmsq_f16(float16x8_t a, float16x8_t b, float16x8_t c) {
return vfmsq_f16(a, b, c);