forked from OSchip/llvm-project
AMDGPU/GlobalISel: Use waterfall loop for buffer_load
This adds support for more complex waterfall loops that need to handle operands > 32-bits, and multiple operands. llvm-svn: 361021
This commit is contained in:
Matt Arsenault
parent
1400a35f71
commit
b3dc73634c
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@ -105,6 +105,69 @@ const RegisterBank &AMDGPURegisterBankInfo::getRegBankFromRegClass(
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return getRegBank(AMDGPU::VGPRRegBankID);
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}
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template <unsigned NumOps>
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RegisterBankInfo::InstructionMappings
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AMDGPURegisterBankInfo::addMappingFromTable(
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const MachineInstr &MI, const MachineRegisterInfo &MRI,
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const std::array<unsigned, NumOps> RegSrcOpIdx,
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ArrayRef<OpRegBankEntry<NumOps>> Table) const {
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InstructionMappings AltMappings;
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SmallVector<const ValueMapping *, 10> Operands(MI.getNumOperands());
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unsigned Sizes[NumOps];
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for (unsigned I = 0; I < NumOps; ++I) {
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unsigned Reg = MI.getOperand(RegSrcOpIdx[I]).getReg();
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Sizes[I] = getSizeInBits(Reg, MRI, *TRI);
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}
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for (unsigned I = 0, E = MI.getNumExplicitDefs(); I != E; ++I) {
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unsigned SizeI = getSizeInBits(MI.getOperand(I).getReg(), MRI, *TRI);
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Operands[I] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, SizeI);
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}
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unsigned MappingID = 0;
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for (const auto &Entry : Table) {
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for (unsigned I = 0; I < NumOps; ++I) {
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int OpIdx = RegSrcOpIdx[I];
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Operands[OpIdx] = AMDGPU::getValueMapping(Entry.RegBanks[I], Sizes[I]);
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}
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AltMappings.push_back(&getInstructionMapping(MappingID++, Entry.Cost,
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getOperandsMapping(Operands),
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Operands.size()));
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}
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return AltMappings;
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}
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RegisterBankInfo::InstructionMappings
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AMDGPURegisterBankInfo::getInstrAlternativeMappingsIntrinsicWSideEffects(
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const MachineInstr &MI, const MachineRegisterInfo &MRI) const {
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switch (MI.getOperand(MI.getNumExplicitDefs()).getIntrinsicID()) {
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case Intrinsic::amdgcn_buffer_load: {
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static const OpRegBankEntry<3> Table[4] = {
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// Perfectly legal.
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{ { AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID }, 1 },
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{ { AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID }, 1 },
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// Waterfall loop needed for rsrc. In the worst case this will execute
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// approximately an extra 10 * wavesize + 2 instructions.
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{ { AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID }, 1000 },
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{ { AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID }, 1000 }
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};
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// rsrc, voffset, offset
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const std::array<unsigned, 3> RegSrcOpIdx = { 2, 3, 4 };
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return addMappingFromTable<3>(MI, MRI, RegSrcOpIdx, makeArrayRef(Table));
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}
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default:
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return RegisterBankInfo::getInstrAlternativeMappings(MI);
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}
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}
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RegisterBankInfo::InstructionMappings
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AMDGPURegisterBankInfo::getInstrAlternativeMappings(
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const MachineInstr &MI) const {
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@ -283,6 +346,8 @@ AMDGPURegisterBankInfo::getInstrAlternativeMappings(
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AltMappings.push_back(&VMapping);
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return AltMappings;
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}
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case AMDGPU::G_INTRINSIC_W_SIDE_EFFECTS:
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return getInstrAlternativeMappingsIntrinsicWSideEffects(MI, MRI);
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default:
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break;
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}
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@ -333,7 +398,21 @@ static LLT getHalfSizedType(LLT Ty) {
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/// Legalize instruction \p MI where operands in \p OpIndices must be SGPRs. If
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/// any of the required SGPR operands are VGPRs, perform a waterfall loop to
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/// execute the instruction for each unique combination of values in all lanes
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/// in the wave. The block will be split such that new blocks
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/// in the wave. The block will be split such that rest of the instructions are
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/// moved to a new block.
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///
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/// Essentially performs this loop:
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//
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/// Save Execution Mask
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/// For (Lane : Wavefront) {
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/// Enable Lane, Disable all other lanes
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/// SGPR = read SGPR value for current lane from VGPR
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/// VGPRResult[Lane] = use_op SGPR
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/// }
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/// Restore Execution Mask
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///
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/// There is additional complexity to try for compare values to identify the
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/// unique values used.
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void AMDGPURegisterBankInfo::executeInWaterfallLoop(
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MachineInstr &MI, MachineRegisterInfo &MRI,
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ArrayRef<unsigned> OpIndices) const {
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@ -345,9 +424,6 @@ void AMDGPURegisterBankInfo::executeInWaterfallLoop(
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MachineBasicBlock &MBB = *MI.getParent();
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const DebugLoc &DL = MI.getDebugLoc();
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assert(OpIndices.size() == 1 &&
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"need to implement support for multiple operands");
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// Use a set to avoid extra readfirstlanes in the case where multiple operands
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// are the same register.
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SmallSet<unsigned, 4> SGPROperandRegs;
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@ -386,13 +462,8 @@ void AMDGPURegisterBankInfo::executeInWaterfallLoop(
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B.buildInstr(TargetOpcode::IMPLICIT_DEF)
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.addDef(InitSaveExecReg);
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// Save the EXEC mask
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BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B64_term), SaveExecReg)
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.addReg(AMDGPU::EXEC);
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unsigned PhiExec = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
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unsigned NewExec = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
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unsigned CondReg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
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// To insert the loop we need to split the block. Move everything before this
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// point to a new block, and insert a new empty block before this instruction.
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@ -437,37 +508,172 @@ void AMDGPURegisterBankInfo::executeInWaterfallLoop(
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LoopBB->splice(LoopBB->end(), &MBB, I);
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I = std::prev(LoopBB->end());
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B.setInstr(*I);
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unsigned CondReg = AMDGPU::NoRegister;
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for (MachineOperand &Op : MI.uses()) {
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if (!Op.isReg())
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continue;
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assert(!Op.isDef());
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if (SGPROperandRegs.count(Op.getReg())) {
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unsigned CurrentLaneOpReg
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= MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
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MRI.setType(CurrentLaneOpReg, LLT::scalar(32)); // FIXME
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LLT OpTy = MRI.getType(Op.getReg());
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unsigned OpSize = OpTy.getSizeInBits();
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assert(MRI.getType(Op.getReg())== LLT::scalar(32) &&
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"need to implement support for other types");
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// Can only do a readlane of 32-bit pieces.
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if (OpSize == 32) {
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// Avoid extra copies in the simple case of one 32-bit register.
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unsigned CurrentLaneOpReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
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MRI.setType(CurrentLaneOpReg, OpTy);
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constrainGenericRegister(Op.getReg(), AMDGPU::VGPR_32RegClass, MRI);
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// Read the next variant <- also loop target.
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BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), CurrentLaneOpReg)
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.addReg(Op.getReg());
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unsigned NewCondReg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
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bool First = CondReg == AMDGPU::NoRegister;
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if (First)
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CondReg = NewCondReg;
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// Compare the just read M0 value to all possible Idx values.
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B.buildInstr(AMDGPU::V_CMP_EQ_U32_e64)
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.addDef(NewCondReg)
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.addReg(CurrentLaneOpReg)
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.addReg(Op.getReg());
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Op.setReg(CurrentLaneOpReg);
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if (!First) {
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unsigned AndReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
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// If there are multiple operands to consider, and the conditions.
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B.buildInstr(AMDGPU::S_AND_B64)
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.addDef(AndReg)
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.addReg(NewCondReg)
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.addReg(CondReg);
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CondReg = AndReg;
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}
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} else {
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LLT S32 = LLT::scalar(32);
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SmallVector<unsigned, 8> ReadlanePieces;
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// The compares can be done as 64-bit, but the extract needs to be done
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// in 32-bit pieces.
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bool Is64 = OpSize % 64 == 0;
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LLT UnmergeTy = OpSize % 64 == 0 ? LLT::scalar(64) : LLT::scalar(32);
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unsigned CmpOp = OpSize % 64 == 0 ? AMDGPU::V_CMP_EQ_U64_e64
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: AMDGPU::V_CMP_EQ_U32_e64;
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// The compares can be done as 64-bit, but the extract needs to be done
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// in 32-bit pieces.
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// Insert the unmerge before the loop.
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B.setMBB(MBB);
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auto Unmerge = B.buildUnmerge(UnmergeTy, Op.getReg());
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B.setInstr(*I);
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unsigned NumPieces = Unmerge->getNumOperands() - 1;
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for (unsigned PieceIdx = 0; PieceIdx != NumPieces; ++PieceIdx) {
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unsigned UnmergePiece = Unmerge.getReg(PieceIdx);
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unsigned CurrentLaneOpReg;
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if (Is64) {
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unsigned CurrentLaneOpRegLo = MRI.createGenericVirtualRegister(S32);
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unsigned CurrentLaneOpRegHi = MRI.createGenericVirtualRegister(S32);
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MRI.setRegClass(UnmergePiece, &AMDGPU::VReg_64RegClass);
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MRI.setRegClass(CurrentLaneOpRegLo, &AMDGPU::SReg_32_XM0RegClass);
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MRI.setRegClass(CurrentLaneOpRegHi, &AMDGPU::SReg_32_XM0RegClass);
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// FIXME: Should be able to just use a subreg index here.
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auto Unmerge32 = B.buildUnmerge(S32, UnmergePiece);
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MRI.setRegClass(Unmerge32.getReg(0), &AMDGPU::VGPR_32RegClass);
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MRI.setRegClass(Unmerge32.getReg(1), &AMDGPU::VGPR_32RegClass);
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// Read the next variant <- also loop target.
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BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32),
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CurrentLaneOpRegLo)
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.addReg(Unmerge32.getReg(0));
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// Read the next variant <- also loop target.
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BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32),
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CurrentLaneOpRegHi)
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.addReg(Unmerge32.getReg(1));
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CurrentLaneOpReg =
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B.buildMerge(LLT::scalar(64),
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{CurrentLaneOpRegLo, CurrentLaneOpRegHi})
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.getReg(0);
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MRI.setRegClass(CurrentLaneOpReg, &AMDGPU::SReg_64_XEXECRegClass);
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if (OpTy.getScalarSizeInBits() == 64) {
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// If we need to produce a 64-bit element vector, so use the
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// merged pieces
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ReadlanePieces.push_back(CurrentLaneOpReg);
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} else {
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// 32-bit element type.
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ReadlanePieces.push_back(CurrentLaneOpRegLo);
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ReadlanePieces.push_back(CurrentLaneOpRegHi);
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}
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} else {
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CurrentLaneOpReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
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MRI.setRegClass(UnmergePiece, &AMDGPU::VGPR_32RegClass);
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MRI.setRegClass(CurrentLaneOpReg, &AMDGPU::SReg_32_XM0RegClass);
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// Read the next variant <- also loop target.
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BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32),
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CurrentLaneOpReg)
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.addReg(Op.getReg());
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.addReg(UnmergePiece);
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ReadlanePieces.push_back(CurrentLaneOpReg);
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}
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// FIXME: Need to and each conditon
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unsigned NewCondReg
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= MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
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bool First = CondReg == AMDGPU::NoRegister;
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if (First)
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CondReg = NewCondReg;
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// Compare the just read SGPR value to all possible operand values.
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B.buildInstr(AMDGPU::V_CMP_EQ_U32_e64)
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.addDef(CondReg)
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B.buildInstr(CmpOp)
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.addDef(NewCondReg)
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.addReg(CurrentLaneOpReg)
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.addReg(Op.getReg());
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Op.setReg(CurrentLaneOpReg);
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.addReg(UnmergePiece);
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if (!First) {
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unsigned AndReg
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= MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
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// If there are multiple operands to consider, and the conditions.
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B.buildInstr(AMDGPU::S_AND_B64)
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.addDef(AndReg)
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.addReg(NewCondReg)
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.addReg(CondReg);
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CondReg = AndReg;
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}
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}
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// FIXME: Build merge seems to switch to CONCAT_VECTORS but not
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// BUILD_VECTOR
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if (OpTy.isVector()) {
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auto Merge = B.buildBuildVector(OpTy, ReadlanePieces);
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Op.setReg(Merge.getReg(0));
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} else {
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auto Merge = B.buildMerge(OpTy, ReadlanePieces);
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Op.setReg(Merge.getReg(0));
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}
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MRI.setRegBank(Op.getReg(), getRegBank(AMDGPU::SGPRRegBankID));
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}
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}
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}
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B.setInsertPt(*LoopBB, LoopBB->end());
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// Update EXEC, save the original EXEC value to VCC.
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B.buildInstr(AMDGPU::S_AND_SAVEEXEC_B64)
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.addDef(NewExec)
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@ -488,7 +694,12 @@ void AMDGPURegisterBankInfo::executeInWaterfallLoop(
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B.buildInstr(AMDGPU::S_CBRANCH_EXECNZ)
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.addMBB(LoopBB);
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// Restore the EXEC mask
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// Save the EXEC mask before the loop.
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BuildMI(MBB, MBB.end(), DL, TII->get(AMDGPU::S_MOV_B64_term), SaveExecReg)
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.addReg(AMDGPU::EXEC);
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// Restore the EXEC mask after the loop.
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B.setMBB(*RestoreExecBB);
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B.buildInstr(AMDGPU::S_MOV_B64_term)
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.addDef(AMDGPU::EXEC)
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.addReg(SaveExecReg);
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@ -606,6 +817,18 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
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applyDefaultMapping(OpdMapper);
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executeInWaterfallLoop(MI, MRI, { 2 });
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return;
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case AMDGPU::G_INTRINSIC_W_SIDE_EFFECTS: {
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switch (MI.getOperand(MI.getNumExplicitDefs()).getIntrinsicID()) {
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case Intrinsic::amdgcn_buffer_load: {
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executeInWaterfallLoop(MI, MRI, { 2 });
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return;
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}
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default:
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break;
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}
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break;
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}
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default:
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break;
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}
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@ -1012,7 +1235,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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break;
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}
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case AMDGPU::G_INTRINSIC: {
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switch (MI.getOperand(1).getIntrinsicID()) {
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switch (MI.getOperand(MI.getNumExplicitDefs()).getIntrinsicID()) {
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default:
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return getInvalidInstructionMapping();
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case Intrinsic::maxnum:
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@ -1034,7 +1257,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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break;
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}
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case AMDGPU::G_INTRINSIC_W_SIDE_EFFECTS: {
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switch (MI.getOperand(0).getIntrinsicID()) {
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switch (MI.getOperand(MI.getNumExplicitDefs()).getIntrinsicID()) {
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default:
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return getInvalidInstructionMapping();
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case Intrinsic::amdgcn_exp_compr:
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@ -1063,7 +1286,33 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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OpdsMapping[7] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
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OpdsMapping[8] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
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break;
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case Intrinsic::amdgcn_buffer_load: {
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unsigned RSrc = MI.getOperand(2).getReg(); // SGPR
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unsigned VIndex = MI.getOperand(3).getReg(); // VGPR
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unsigned Offset = MI.getOperand(4).getReg(); // SGPR/VGPR/imm
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unsigned Size0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
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unsigned Size2 = MRI.getType(RSrc).getSizeInBits();
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unsigned Size3 = MRI.getType(VIndex).getSizeInBits();
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unsigned Size4 = MRI.getType(Offset).getSizeInBits();
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unsigned RSrcBank = getRegBankID(RSrc, MRI, *TRI);
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unsigned OffsetBank = getRegBankID(Offset, MRI, *TRI);
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OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size0);
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OpdsMapping[1] = nullptr; // intrinsic id
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// Lie and claim everything is legal, even though some need to be
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// SGPRs. applyMapping will have to deal with it as a waterfall loop.
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OpdsMapping[2] = AMDGPU::getValueMapping(RSrcBank, Size2); // rsrc
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OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size3);
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OpdsMapping[4] = AMDGPU::getValueMapping(OffsetBank, Size4);
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OpdsMapping[5] = nullptr;
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OpdsMapping[6] = nullptr;
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break;
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}
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}
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break;
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}
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case AMDGPU::G_SELECT: {
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@ -1121,7 +1370,8 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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}
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}
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return getInstructionMapping(1, 1, getOperandsMapping(OpdsMapping),
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return getInstructionMapping(/*ID*/1, /*Cost*/1,
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getOperandsMapping(OpdsMapping),
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MI.getNumOperands());
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}
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@ -58,6 +58,22 @@ class AMDGPURegisterBankInfo : public AMDGPUGenRegisterBankInfo {
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LLT HalfTy,
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unsigned Reg) const;
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template <unsigned NumOps>
|
||||
struct OpRegBankEntry {
|
||||
int8_t RegBanks[NumOps];
|
||||
int16_t Cost;
|
||||
};
|
||||
|
||||
template <unsigned NumOps>
|
||||
InstructionMappings
|
||||
addMappingFromTable(const MachineInstr &MI, const MachineRegisterInfo &MRI,
|
||||
const std::array<unsigned, NumOps> RegSrcOpIdx,
|
||||
ArrayRef<OpRegBankEntry<NumOps>> Table) const;
|
||||
|
||||
RegisterBankInfo::InstructionMappings
|
||||
getInstrAlternativeMappingsIntrinsicWSideEffects(
|
||||
const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
|
||||
|
||||
bool isSALUMapping(const MachineInstr &MI) const;
|
||||
const InstructionMapping &getDefaultMappingSOP(const MachineInstr &MI) const;
|
||||
const InstructionMapping &getDefaultMappingVOP(const MachineInstr &MI) const;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,289 @@
|
|||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs %s -o - | FileCheck %s
|
||||
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs %s -o - | FileCheck %s
|
||||
|
||||
---
|
||||
name: buffer_load_sss
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, $sgpr5
|
||||
|
||||
; CHECK-LABEL: name: buffer_load_sss
|
||||
; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, $sgpr5
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
|
||||
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
|
||||
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; CHECK: [[INT:%[0-9]+]]:vgpr(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.buffer.load), [[COPY]](<4 x s32>), [[COPY1]](s32), [[COPY2]](s32), 0, 0
|
||||
%0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
%1:_(s32) = COPY $sgpr4
|
||||
%2:_(s32) = COPY $sgpr5
|
||||
%3:_(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.buffer.load), %0, %1, %2, 0, 0
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
name: buffer_load_ssv
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, $vgpr5
|
||||
|
||||
; CHECK-LABEL: name: buffer_load_ssv
|
||||
; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, $vgpr5
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
|
||||
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr5
|
||||
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; CHECK: [[INT:%[0-9]+]]:vgpr(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.buffer.load), [[COPY]](<4 x s32>), [[COPY1]](s32), [[COPY2]](s32), 0, 0
|
||||
%0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
%1:_(s32) = COPY $sgpr4
|
||||
%2:_(s32) = COPY $vgpr5
|
||||
%3:_(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.buffer.load), %0, %1, %2, 0, 0
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
name: buffer_load_svs
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, $sgpr5
|
||||
|
||||
; CHECK-LABEL: name: buffer_load_svs
|
||||
; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, $sgpr5
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
|
||||
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
|
||||
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; CHECK: [[INT:%[0-9]+]]:vgpr(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.buffer.load), [[COPY]](<4 x s32>), [[COPY1]](s32), [[COPY2]](s32), 0, 0
|
||||
%0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
%1:_(s32) = COPY $sgpr4
|
||||
%2:_(s32) = COPY $sgpr5
|
||||
%3:_(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.buffer.load), %0, %1, %2, 0, 0
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
name: buffer_load_vss
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr4, $sgpr5
|
||||
|
||||
; CHECK-LABEL: name: buffer_load_vss
|
||||
; CHECK: successors: %bb.1(0x80000000)
|
||||
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr4, $sgpr5
|
||||
; CHECK: [[COPY:%[0-9]+]]:vgpr(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
|
||||
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
|
||||
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; CHECK: [[DEF:%[0-9]+]]:vgpr(<4 x s32>) = G_IMPLICIT_DEF
|
||||
; CHECK: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; CHECK: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
|
||||
; CHECK: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK: .1:
|
||||
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
; CHECK: [[PHI:%[0-9]+]]:sreg_64 = PHI [[DEF1]], %bb.0, %10, %bb.1
|
||||
; CHECK: [[PHI1:%[0-9]+]]:vgpr(<4 x s32>) = G_PHI [[DEF]](<4 x s32>), %bb.0, %3(<4 x s32>), %bb.1
|
||||
; CHECK: [[UV2:%[0-9]+]]:vgpr_32(s32), [[UV3:%[0-9]+]]:vgpr_32(s32) = G_UNMERGE_VALUES [[UV]](s64)
|
||||
; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV2]](s32), implicit $exec
|
||||
; CHECK: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV3]](s32), implicit $exec
|
||||
; CHECK: [[MV:%[0-9]+]]:sreg_64_xexec(s64) = G_MERGE_VALUES [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32)
|
||||
; CHECK: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[MV]](s64), [[UV]](s64), implicit $exec
|
||||
; CHECK: [[UV4:%[0-9]+]]:vgpr_32(s32), [[UV5:%[0-9]+]]:vgpr_32(s32) = G_UNMERGE_VALUES [[UV1]](s64)
|
||||
; CHECK: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV4]](s32), implicit $exec
|
||||
; CHECK: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV5]](s32), implicit $exec
|
||||
; CHECK: [[MV1:%[0-9]+]]:sreg_64_xexec(s64) = G_MERGE_VALUES [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32)
|
||||
; CHECK: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[MV1]](s64), [[UV1]](s64), implicit $exec
|
||||
; CHECK: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
|
||||
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32)
|
||||
; CHECK: [[INT:%[0-9]+]]:vgpr(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.buffer.load), [[BUILD_VECTOR]](<4 x s32>), [[COPY1]](s32), [[COPY2]](s32), 0, 0
|
||||
; CHECK: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64 = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
|
||||
; CHECK: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
|
||||
; CHECK: S_CBRANCH_EXECNZ %bb.1, implicit $exec
|
||||
; CHECK: .2:
|
||||
; CHECK: successors: %bb.3(0x80000000)
|
||||
; CHECK: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK: .3:
|
||||
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
|
||||
%1:_(s32) = COPY $sgpr4
|
||||
%2:_(s32) = COPY $sgpr5
|
||||
%3:_(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.buffer.load), %0, %1, %2, 0, 0
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
name: buffer_load_vvs
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4, $sgpr5
|
||||
|
||||
; CHECK-LABEL: name: buffer_load_vvs
|
||||
; CHECK: successors: %bb.1(0x80000000)
|
||||
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4, $sgpr5
|
||||
; CHECK: [[COPY:%[0-9]+]]:vgpr(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
|
||||
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr4
|
||||
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
|
||||
; CHECK: [[DEF:%[0-9]+]]:vgpr(<4 x s32>) = G_IMPLICIT_DEF
|
||||
; CHECK: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; CHECK: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
|
||||
; CHECK: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK: .1:
|
||||
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
; CHECK: [[PHI:%[0-9]+]]:sreg_64 = PHI [[DEF1]], %bb.0, %9, %bb.1
|
||||
; CHECK: [[PHI1:%[0-9]+]]:vgpr(<4 x s32>) = G_PHI [[DEF]](<4 x s32>), %bb.0, %3(<4 x s32>), %bb.1
|
||||
; CHECK: [[UV2:%[0-9]+]]:vgpr_32(s32), [[UV3:%[0-9]+]]:vgpr_32(s32) = G_UNMERGE_VALUES [[UV]](s64)
|
||||
; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV2]](s32), implicit $exec
|
||||
; CHECK: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV3]](s32), implicit $exec
|
||||
; CHECK: [[MV:%[0-9]+]]:sreg_64_xexec(s64) = G_MERGE_VALUES [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32)
|
||||
; CHECK: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[MV]](s64), [[UV]](s64), implicit $exec
|
||||
; CHECK: [[UV4:%[0-9]+]]:vgpr_32(s32), [[UV5:%[0-9]+]]:vgpr_32(s32) = G_UNMERGE_VALUES [[UV1]](s64)
|
||||
; CHECK: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV4]](s32), implicit $exec
|
||||
; CHECK: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV5]](s32), implicit $exec
|
||||
; CHECK: [[MV1:%[0-9]+]]:sreg_64_xexec(s64) = G_MERGE_VALUES [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32)
|
||||
; CHECK: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[MV1]](s64), [[UV1]](s64), implicit $exec
|
||||
; CHECK: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
|
||||
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32)
|
||||
; CHECK: [[INT:%[0-9]+]]:vgpr(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.buffer.load), [[BUILD_VECTOR]](<4 x s32>), [[COPY1]](s32), [[COPY2]](s32), 0, 0
|
||||
; CHECK: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64 = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
|
||||
; CHECK: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
|
||||
; CHECK: S_CBRANCH_EXECNZ %bb.1, implicit $exec
|
||||
; CHECK: .2:
|
||||
; CHECK: successors: %bb.3(0x80000000)
|
||||
; CHECK: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK: .3:
|
||||
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
|
||||
%1:_(s32) = COPY $vgpr4
|
||||
%2:_(s32) = COPY $sgpr5
|
||||
%3:_(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.buffer.load), %0, %1, %2, 0, 0
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
name: buffer_load_svv
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $vgpr4, $vgpr5
|
||||
|
||||
; CHECK-LABEL: name: buffer_load_svv
|
||||
; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $vgpr4, $vgpr5
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr4
|
||||
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr5
|
||||
; CHECK: [[INT:%[0-9]+]]:vgpr(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.buffer.load), [[COPY]](<4 x s32>), [[COPY1]](s32), [[COPY2]](s32), 0, 0
|
||||
%0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
%1:_(s32) = COPY $vgpr4
|
||||
%2:_(s32) = COPY $vgpr5
|
||||
%3:_(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.buffer.load), %0, %1, %2, 0, 0
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
name: buffer_load_vsv
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr4, $vgpr5
|
||||
|
||||
; CHECK-LABEL: name: buffer_load_vsv
|
||||
; CHECK: successors: %bb.1(0x80000000)
|
||||
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr4, $vgpr5
|
||||
; CHECK: [[COPY:%[0-9]+]]:vgpr(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
|
||||
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr5
|
||||
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; CHECK: [[DEF:%[0-9]+]]:vgpr(<4 x s32>) = G_IMPLICIT_DEF
|
||||
; CHECK: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; CHECK: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
|
||||
; CHECK: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK: .1:
|
||||
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
; CHECK: [[PHI:%[0-9]+]]:sreg_64 = PHI [[DEF1]], %bb.0, %10, %bb.1
|
||||
; CHECK: [[PHI1:%[0-9]+]]:vgpr(<4 x s32>) = G_PHI [[DEF]](<4 x s32>), %bb.0, %3(<4 x s32>), %bb.1
|
||||
; CHECK: [[UV2:%[0-9]+]]:vgpr_32(s32), [[UV3:%[0-9]+]]:vgpr_32(s32) = G_UNMERGE_VALUES [[UV]](s64)
|
||||
; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV2]](s32), implicit $exec
|
||||
; CHECK: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV3]](s32), implicit $exec
|
||||
; CHECK: [[MV:%[0-9]+]]:sreg_64_xexec(s64) = G_MERGE_VALUES [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32)
|
||||
; CHECK: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[MV]](s64), [[UV]](s64), implicit $exec
|
||||
; CHECK: [[UV4:%[0-9]+]]:vgpr_32(s32), [[UV5:%[0-9]+]]:vgpr_32(s32) = G_UNMERGE_VALUES [[UV1]](s64)
|
||||
; CHECK: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV4]](s32), implicit $exec
|
||||
; CHECK: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV5]](s32), implicit $exec
|
||||
; CHECK: [[MV1:%[0-9]+]]:sreg_64_xexec(s64) = G_MERGE_VALUES [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32)
|
||||
; CHECK: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[MV1]](s64), [[UV1]](s64), implicit $exec
|
||||
; CHECK: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
|
||||
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32)
|
||||
; CHECK: [[INT:%[0-9]+]]:vgpr(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.buffer.load), [[BUILD_VECTOR]](<4 x s32>), [[COPY1]](s32), [[COPY2]](s32), 0, 0
|
||||
; CHECK: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64 = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
|
||||
; CHECK: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
|
||||
; CHECK: S_CBRANCH_EXECNZ %bb.1, implicit $exec
|
||||
; CHECK: .2:
|
||||
; CHECK: successors: %bb.3(0x80000000)
|
||||
; CHECK: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK: .3:
|
||||
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
|
||||
%1:_(s32) = COPY $sgpr4
|
||||
%2:_(s32) = COPY $vgpr5
|
||||
%3:_(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.buffer.load), %0, %1, %2, 0, 0
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
name: buffer_load_vvv
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4, $vgpr5
|
||||
|
||||
; CHECK-LABEL: name: buffer_load_vvv
|
||||
; CHECK: successors: %bb.1(0x80000000)
|
||||
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4, $vgpr5
|
||||
; CHECK: [[COPY:%[0-9]+]]:vgpr(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
|
||||
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr4
|
||||
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr5
|
||||
; CHECK: [[DEF:%[0-9]+]]:vgpr(<4 x s32>) = G_IMPLICIT_DEF
|
||||
; CHECK: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; CHECK: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
|
||||
; CHECK: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK: .1:
|
||||
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
; CHECK: [[PHI:%[0-9]+]]:sreg_64 = PHI [[DEF1]], %bb.0, %9, %bb.1
|
||||
; CHECK: [[PHI1:%[0-9]+]]:vgpr(<4 x s32>) = G_PHI [[DEF]](<4 x s32>), %bb.0, %3(<4 x s32>), %bb.1
|
||||
; CHECK: [[UV2:%[0-9]+]]:vgpr_32(s32), [[UV3:%[0-9]+]]:vgpr_32(s32) = G_UNMERGE_VALUES [[UV]](s64)
|
||||
; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV2]](s32), implicit $exec
|
||||
; CHECK: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV3]](s32), implicit $exec
|
||||
; CHECK: [[MV:%[0-9]+]]:sreg_64_xexec(s64) = G_MERGE_VALUES [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32)
|
||||
; CHECK: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[MV]](s64), [[UV]](s64), implicit $exec
|
||||
; CHECK: [[UV4:%[0-9]+]]:vgpr_32(s32), [[UV5:%[0-9]+]]:vgpr_32(s32) = G_UNMERGE_VALUES [[UV1]](s64)
|
||||
; CHECK: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV4]](s32), implicit $exec
|
||||
; CHECK: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV5]](s32), implicit $exec
|
||||
; CHECK: [[MV1:%[0-9]+]]:sreg_64_xexec(s64) = G_MERGE_VALUES [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32)
|
||||
; CHECK: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[MV1]](s64), [[UV1]](s64), implicit $exec
|
||||
; CHECK: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
|
||||
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32)
|
||||
; CHECK: [[INT:%[0-9]+]]:vgpr(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.buffer.load), [[BUILD_VECTOR]](<4 x s32>), [[COPY1]](s32), [[COPY2]](s32), 0, 0
|
||||
; CHECK: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64 = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
|
||||
; CHECK: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
|
||||
; CHECK: S_CBRANCH_EXECNZ %bb.1, implicit $exec
|
||||
; CHECK: .2:
|
||||
; CHECK: successors: %bb.3(0x80000000)
|
||||
; CHECK: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK: .3:
|
||||
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
|
||||
%1:_(s32) = COPY $vgpr4
|
||||
%2:_(s32) = COPY $vgpr5
|
||||
%3:_(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.buffer.load), %0, %1, %2, 0, 0
|
||||
|
||||
...
|
||||
|
||||
|
|
@ -44,14 +44,14 @@ body: |
|
|||
; CHECK: [[PHI:%[0-9]+]]:sreg_64 = PHI [[DEF1]], %bb.0, %9, %bb.1
|
||||
; CHECK: [[PHI1:%[0-9]+]]:vgpr(s32) = G_PHI [[DEF]](s32), %bb.0, %2(s32), %bb.1
|
||||
; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[COPY1]](s32), implicit $exec
|
||||
; CHECK: [[EVEC:%[0-9]+]]:vgpr(s32) = G_EXTRACT_VECTOR_ELT [[COPY2]](<16 x s32>), [[V_READFIRSTLANE_B32_]](s32)
|
||||
; CHECK: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_]](s32), [[COPY1]](s32), implicit $exec
|
||||
; CHECK: [[EVEC:%[0-9]+]]:vgpr(s32) = G_EXTRACT_VECTOR_ELT [[COPY2]](<16 x s32>), [[V_READFIRSTLANE_B32_]](s32)
|
||||
; CHECK: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64 = S_AND_SAVEEXEC_B64 killed [[V_CMP_EQ_U32_e64_]], implicit-def $exec, implicit-def $scc, implicit $exec
|
||||
; CHECK: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
|
||||
; CHECK: S_CBRANCH_EXECNZ %bb.1, implicit $exec
|
||||
; CHECK: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK: .2:
|
||||
; CHECK: successors: %bb.3(0x80000000)
|
||||
; CHECK: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK: .3:
|
||||
; CHECK: $vgpr0 = COPY [[EVEC]](s32)
|
||||
%0:_(<16 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
|
||||
|
|
@ -101,14 +101,14 @@ body: |
|
|||
; CHECK: [[PHI:%[0-9]+]]:sreg_64 = PHI [[DEF1]], %bb.0, %8, %bb.1
|
||||
; CHECK: [[PHI1:%[0-9]+]]:vgpr(s32) = G_PHI [[DEF]](s32), %bb.0, %2(s32), %bb.1
|
||||
; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[COPY1]](s32), implicit $exec
|
||||
; CHECK: [[EVEC:%[0-9]+]]:vgpr(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<16 x s32>), [[V_READFIRSTLANE_B32_]](s32)
|
||||
; CHECK: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_]](s32), [[COPY1]](s32), implicit $exec
|
||||
; CHECK: [[EVEC:%[0-9]+]]:vgpr(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<16 x s32>), [[V_READFIRSTLANE_B32_]](s32)
|
||||
; CHECK: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64 = S_AND_SAVEEXEC_B64 killed [[V_CMP_EQ_U32_e64_]], implicit-def $exec, implicit-def $scc, implicit $exec
|
||||
; CHECK: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
|
||||
; CHECK: S_CBRANCH_EXECNZ %bb.1, implicit $exec
|
||||
; CHECK: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK: .2:
|
||||
; CHECK: successors: %bb.3(0x80000000)
|
||||
; CHECK: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK: .3:
|
||||
; CHECK: $vgpr0 = COPY [[EVEC]](s32)
|
||||
%0:_(<16 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
||||
|
|
@ -138,14 +138,14 @@ body: |
|
|||
; CHECK: [[PHI:%[0-9]+]]:sreg_64 = PHI [[DEF1]], %bb.0, %8, %bb.1
|
||||
; CHECK: [[PHI1:%[0-9]+]]:vgpr(s64) = G_PHI [[DEF]](s64), %bb.0, %2(s64), %bb.1
|
||||
; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[COPY1]](s32), implicit $exec
|
||||
; CHECK: [[EVEC:%[0-9]+]]:vgpr(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](<8 x s64>), [[V_READFIRSTLANE_B32_]](s32)
|
||||
; CHECK: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_]](s32), [[COPY1]](s32), implicit $exec
|
||||
; CHECK: [[EVEC:%[0-9]+]]:vgpr(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](<8 x s64>), [[V_READFIRSTLANE_B32_]](s32)
|
||||
; CHECK: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64 = S_AND_SAVEEXEC_B64 killed [[V_CMP_EQ_U32_e64_]], implicit-def $exec, implicit-def $scc, implicit $exec
|
||||
; CHECK: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
|
||||
; CHECK: S_CBRANCH_EXECNZ %bb.1, implicit $exec
|
||||
; CHECK: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK: .2:
|
||||
; CHECK: successors: %bb.3(0x80000000)
|
||||
; CHECK: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK: .3:
|
||||
; CHECK: $vgpr0_vgpr1 = COPY [[EVEC]](s64)
|
||||
%0:_(<8 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
||||
|
|
|
|||
Loading…
Reference in New Issue