forked from OSchip/llvm-project
[mips] Range check simm32 and fold MIPS16's imm32 into simm32.
Summary: At this point we should be able to enable IAS by default for O32 without breaking check-all, or recursion. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18439 llvm-svn: 265302
This commit is contained in:
Daniel Sanders
parent
cacd94e242
commit
b3c2764f89
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@ -3815,6 +3815,10 @@ bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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case Match_UImm26_0:
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return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
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"expected 26-bit unsigned immediate");
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case Match_SImm32:
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case Match_SImm32_Relaxed:
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return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
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"expected 32-bit signed immediate");
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case Match_MemSImm9:
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return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
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"expected memory with 9-bit signed offset");
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@ -483,13 +483,11 @@ class SelT<string op1, string op2>:
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//
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// 32 bit constant
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//
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def imm32: Operand<i32>;
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def Constant32:
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MipsPseudo16<(outs), (ins imm32:$imm), "\t.word $imm", []>;
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MipsPseudo16<(outs), (ins simm32:$imm), "\t.word $imm", []>;
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def LwConstant32:
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MipsPseudo16<(outs CPU16Regs:$rx), (ins imm32:$imm, imm32:$constid),
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MipsPseudo16<(outs CPU16Regs:$rx), (ins simm32:$imm, simm32:$constid),
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"lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>;
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@ -462,8 +462,16 @@ class UImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = []>
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// uimm5 < uimm5_64, and uimm5 < vsplat_uimm5
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// This is entirely arbitrary. We need an ordering and what we pick is
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// unimportant since only one is possible for a given mnemonic.
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def SImm32RelaxedAsmOperandClass
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: SImmAsmOperandClass<32, []> {
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let Name = "SImm32_Relaxed";
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let PredicateMethod = "isAnyImm<32>";
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let DiagnosticType = "SImm32_Relaxed";
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}
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def SImm32AsmOperandClass
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: SImmAsmOperandClass<32, [SImm32RelaxedAsmOperandClass]>;
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def ConstantUImm26AsmOperandClass
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: ConstantUImmAsmOperandClass<26, []>;
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: ConstantUImmAsmOperandClass<26, [SImm32AsmOperandClass]>;
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def ConstantUImm20AsmOperandClass
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: ConstantUImmAsmOperandClass<20, [ConstantUImm26AsmOperandClass]>;
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def UImm16RelaxedAsmOperandClass
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@ -629,8 +637,6 @@ def simm18_lsl3 : Operand<i32> {
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let ParserMatchClass = MipsJumpTargetAsmOperand;
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}
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def simm32 : Operand<i32>;
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// Zero
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def uimmz : Operand<i32> {
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let PrintMethod = "printUImm<0>";
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@ -805,10 +811,11 @@ def simm7_lsl2 : Operand<OtherVT> {
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let ParserMatchClass = ConstantSImm7Lsl2AsmOperandClass;
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}
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def simm16 : Operand<i32> {
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let DecoderMethod = "DecodeSImmWithOffsetAndScale<16>";
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let ParserMatchClass = !cast<AsmOperandClass>("SImm16AsmOperandClass");
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}
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foreach I = {16, 32} in
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def simm # I : Operand<i32> {
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let DecoderMethod = "DecodeSImmWithOffsetAndScale<" # I # ">";
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let ParserMatchClass = !cast<AsmOperandClass>("SImm" # I # "AsmOperandClass");
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}
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// Like simm16 but coerces uimm16 to simm16.
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def simm16_relaxed : Operand<i32> {
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@ -821,6 +828,12 @@ def simm16_64 : Operand<i64> {
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let ParserMatchClass = !cast<AsmOperandClass>("SImm16AsmOperandClass");
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}
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// Like simm32 but coerces uimm32 to simm32.
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def simm32_relaxed : Operand<i32> {
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let DecoderMethod = "DecodeSImmWithOffsetAndScale<32>";
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let ParserMatchClass = !cast<AsmOperandClass>("SImm32RelaxedAsmOperandClass");
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}
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// This is almost the same as a uimm7 but 0x7f is interpreted as -1.
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def li16_imm : Operand<i32> {
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let DecoderMethod = "DecodeLi16Imm";
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@ -2139,20 +2152,26 @@ def : MipsInstAlias<"move $dst, $src",
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}
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def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>,
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ISA_MIPS1_NOT_32R6_64R6;
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def : MipsInstAlias<"addu $rs, $rt, $imm",
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(ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm32:$imm), 0>;
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def : MipsInstAlias<"addu $rs, $imm",
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(ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm32:$imm), 0>;
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def : MipsInstAlias<"add $rs, $rt, $imm",
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(ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32:$imm), 0>,
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ISA_MIPS1_NOT_32R6_64R6;
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def : MipsInstAlias<"add $rs, $imm",
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(ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32:$imm), 0>,
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ISA_MIPS1_NOT_32R6_64R6;
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def : MipsInstAlias<"and $rs, $rt, $imm",
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(ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32:$imm), 0>;
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def : MipsInstAlias<"and $rs, $imm",
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(ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32:$imm), 0>;
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def : MipsInstAlias<
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"addu $rs, $rt, $imm",
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(ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
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def : MipsInstAlias<
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"addu $rs, $imm",
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(ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
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def : MipsInstAlias<
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"add $rs, $rt, $imm",
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(ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>,
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ISA_MIPS1_NOT_32R6_64R6;
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def : MipsInstAlias<
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"add $rs, $imm",
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(ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>,
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ISA_MIPS1_NOT_32R6_64R6;
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def : MipsInstAlias<
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"and $rs, $rt, $imm",
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(ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
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def : MipsInstAlias<
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"and $rs, $imm",
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(ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
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def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
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let Predicates = [NotInMicroMips] in {
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def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
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@ -2166,18 +2185,24 @@ def : MipsInstAlias<"negu $rt",
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(SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
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def : MipsInstAlias<"negu $rt, $rs",
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(SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
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def : MipsInstAlias<"slt $rs, $rt, $imm",
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(SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32:$imm), 0>;
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def : MipsInstAlias<"sltu $rt, $rs, $imm",
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(SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm32:$imm), 0>;
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def : MipsInstAlias<"xor $rs, $rt, $imm",
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(XORi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32:$imm), 0>;
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def : MipsInstAlias<"xor $rs, $imm",
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(XORi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32:$imm), 0>;
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def : MipsInstAlias<"or $rs, $rt, $imm",
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(ORi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32:$imm), 0>;
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def : MipsInstAlias<"or $rs, $imm",
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(ORi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32:$imm), 0>;
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def : MipsInstAlias<
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"slt $rs, $rt, $imm",
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(SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
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def : MipsInstAlias<
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"sltu $rt, $rs, $imm",
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(SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
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def : MipsInstAlias<
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"xor $rs, $rt, $imm",
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(XORi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
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def : MipsInstAlias<
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"xor $rs, $imm",
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(XORi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
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def : MipsInstAlias<
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"or $rs, $rt, $imm",
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(ORi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
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def : MipsInstAlias<
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"or $rs, $imm",
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(ORi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
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let AdditionalPredicates = [NotInMicroMips] in {
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def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
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}
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@ -2242,10 +2267,11 @@ def : MipsInstAlias<"sync",
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// Assembler Pseudo Instructions
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//===----------------------------------------------------------------------===//
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// We use i32imm on li/la to defer range checking to the assembler.
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class LoadImmediate32<string instr_asm, Operand Od, RegisterOperand RO> :
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MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
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!strconcat(instr_asm, "\t$rt, $imm32")> ;
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def LoadImm32 : LoadImmediate32<"li", simm32, GPR32Opnd>;
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def LoadImm32 : LoadImmediate32<"li", i32imm, GPR32Opnd>;
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class LoadAddressFromReg32<string instr_asm, Operand MemOpnd,
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RegisterOperand RO> :
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@ -2256,7 +2282,7 @@ def LoadAddrReg32 : LoadAddressFromReg32<"la", mem, GPR32Opnd>;
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class LoadAddressFromImm32<string instr_asm, Operand Od, RegisterOperand RO> :
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MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
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!strconcat(instr_asm, "\t$rt, $imm32")> ;
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def LoadAddrImm32 : LoadAddressFromImm32<"la", simm32, GPR32Opnd>;
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def LoadAddrImm32 : LoadAddressFromImm32<"la", i32imm, GPR32Opnd>;
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def JalTwoReg : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs),
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"jal\t$rd, $rs"> ;
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@ -22,8 +22,7 @@ text_label:
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# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c]
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# CHECK: add $4, $4, $1 # encoding: [0x20,0x20,0x81,0x00]
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add $4, 0xFFFFFFFF
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# CHECK: addiu $1, $zero, -1 # encoding: [0xff,0xff,0x01,0x24]
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# CHECK: add $4, $4, $1 # encoding: [0x20,0x20,0x81,0x00]
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# CHECK: addi $4, $4, -1 # encoding: [0xff,0xff,0x84,0x20]
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add $4, $5, -0x80000000
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# CHECK: lui $4, 32768 # encoding: [0x00,0x80,0x04,0x3c]
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@ -43,8 +42,7 @@ text_label:
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# CHECK: lui $4, 1 # encoding: [0x01,0x00,0x04,0x3c]
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# CHECK: add $4, $4, $5 # encoding: [0x20,0x20,0x85,0x00]
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add $4, $5, 0xFFFFFFFF
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# CHECK: addiu $4, $zero, -1 # encoding: [0xff,0xff,0x04,0x24]
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# CHECK: add $4, $4, $5 # encoding: [0x20,0x20,0x85,0x00]
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# CHECK: addi $4, $5, -1 # encoding: [0xff,0xff,0xa4,0x20]
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addu $4, -0x80000000
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# CHECK: lui $1, 32768 # encoding: [0x00,0x80,0x01,0x3c]
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@ -64,8 +62,7 @@ text_label:
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# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c]
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# CHECK: addu $4, $4, $1 # encoding: [0x21,0x20,0x81,0x00]
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addu $4, 0xFFFFFFFF
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# CHECK: addiu $1, $zero, -1 # encoding: [0xff,0xff,0x01,0x24]
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# CHECK: addu $4, $4, $1 # encoding: [0x21,0x20,0x81,0x00]
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# CHECK: addiu $4, $4, -1 # encoding: [0xff,0xff,0x84,0x24]
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addu $4, $5, -0x80000000
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# CHECK: lui $4, 32768 # encoding: [0x00,0x80,0x04,0x3c]
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@ -85,8 +82,7 @@ text_label:
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# CHECK: lui $4, 1 # encoding: [0x01,0x00,0x04,0x3c]
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# CHECK: addu $4, $4, $5 # encoding: [0x21,0x20,0x85,0x00]
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addu $4, $5, 0xFFFFFFFF
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# CHECK: addiu $4, $zero, -1 # encoding: [0xff,0xff,0x04,0x24]
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# CHECK: addu $4, $4, $5 # encoding: [0x21,0x20,0x85,0x00]
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# CHECK: addiu $4, $5, -1 # encoding: [0xff,0xff,0xa4,0x24]
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and $4, -0x80000000
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# CHECK: lui $1, 32768 # encoding: [0x00,0x80,0x01,0x3c]
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@ -208,8 +204,7 @@ text_label:
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# CHECK: lui $4, 1 # encoding: [0x01,0x00,0x04,0x3c]
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# CHECK: slt $4, $4, $5 # encoding: [0x2a,0x20,0x85,0x00]
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slt $4, $5, 0xFFFFFFFF
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# CHECK: addiu $4, $zero, -1 # encoding: [0xff,0xff,0x04,0x24]
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# CHECK: slt $4, $4, $5 # encoding: [0x2a,0x20,0x85,0x00]
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# CHECK: slti $4, $5, -1 # encoding: [0xff,0xff,0xa4,0x28]
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sltu $4, $5, -0x80000000
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# CHECK: lui $4, 32768 # encoding: [0x00,0x80,0x04,0x3c]
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@ -228,8 +223,7 @@ text_label:
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# CHECK: lui $4, 1 # encoding: [0x01,0x00,0x04,0x3c]
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# CHECK: sltu $4, $4, $5 # encoding: [0x2b,0x20,0x85,0x00]
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sltu $4, $5, 0xFFFFFFFF
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# CHECK: addiu $4, $zero, -1 # encoding: [0xff,0xff,0x04,0x24]
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# CHECK: sltu $4, $4, $5 # encoding: [0x2b,0x20,0x85,0x00]
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# CHECK: sltiu $4, $5, -1 # encoding: [0xff,0xff,0xa4,0x2c]
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xor $4, -0x80000000
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# CHECK: lui $1, 32768 # encoding: [0x00,0x80,0x01,0x3c]
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