forked from OSchip/llvm-project
[NFC] Refine some uninitialized used variables.
These warning are reported by static code analysis tool: Klocwork Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D95421
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@ -2697,7 +2697,7 @@ const BlockByrefInfo &CodeGenFunction::getBlockByrefInfo(const VarDecl *D) {
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}
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bool HasByrefExtendedLayout = false;
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Qualifiers::ObjCLifetime Lifetime;
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Qualifiers::ObjCLifetime Lifetime = Qualifiers::OCL_None;
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if (getContext().getByrefLifetime(Ty, Lifetime, HasByrefExtendedLayout) &&
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HasByrefExtendedLayout) {
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/// void *__byref_variable_layout;
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@ -2767,8 +2767,8 @@ void CodeGenFunction::emitByrefStructureInit(const AutoVarEmission &emission) {
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const VarDecl &D = *emission.Variable;
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QualType type = D.getType();
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bool HasByrefExtendedLayout;
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Qualifiers::ObjCLifetime ByrefLifetime;
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bool HasByrefExtendedLayout = false;
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Qualifiers::ObjCLifetime ByrefLifetime = Qualifiers::OCL_None;
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bool ByRefHasLifetime =
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getContext().getByrefLifetime(type, ByrefLifetime, HasByrefExtendedLayout);
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@ -442,7 +442,7 @@ bool CoalescerPair::setRegisters(const MachineInstr *MI) {
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Flipped = CrossClass = false;
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Register Src, Dst;
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unsigned SrcSub, DstSub;
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unsigned SrcSub = 0, DstSub = 0;
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if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
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return false;
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Partial = SrcSub || DstSub;
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@ -537,7 +537,7 @@ bool CoalescerPair::isCoalescable(const MachineInstr *MI) const {
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if (!MI)
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return false;
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Register Src, Dst;
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unsigned SrcSub, DstSub;
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unsigned SrcSub = 0, DstSub = 0;
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if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
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return false;
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@ -1590,7 +1590,7 @@ MachineInstr *RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI) {
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// CoalescerPair may have a new register class with adjusted subreg indices
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// at this point.
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Register SrcReg, DstReg;
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unsigned SrcSubIdx, DstSubIdx;
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unsigned SrcSubIdx = 0, DstSubIdx = 0;
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if(!isMoveInstr(*TRI, CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
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return nullptr;
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@ -1966,7 +1966,7 @@ bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) {
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if (!canJoinPhys(CP)) {
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// Before giving up coalescing, if definition of source is defined by
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// trivial computation, try rematerializing it.
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bool IsDefCopy;
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bool IsDefCopy = false;
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if (reMaterializeTrivialDef(CP, CopyMI, IsDefCopy))
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return true;
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if (IsDefCopy)
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@ -2005,7 +2005,7 @@ bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) {
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// If definition of source is defined by trivial computation, try
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// rematerializing it.
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bool IsDefCopy;
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bool IsDefCopy = false;
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if (reMaterializeTrivialDef(CP, CopyMI, IsDefCopy))
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return true;
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@ -3798,7 +3798,7 @@ bool RegisterCoalescer::applyTerminalRule(const MachineInstr &Copy) const {
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if (!UseTerminalRule)
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return false;
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Register SrcReg, DstReg;
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unsigned SrcSubReg, DstSubReg;
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unsigned SrcSubReg = 0, DstSubReg = 0;
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if (!isMoveInstr(*TRI, &Copy, SrcReg, DstReg, SrcSubReg, DstSubReg))
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return false;
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// Check if the destination of this copy has any other affinity.
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@ -3823,7 +3823,7 @@ bool RegisterCoalescer::applyTerminalRule(const MachineInstr &Copy) const {
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if (&MI == &Copy || !MI.isCopyLike() || MI.getParent() != OrigBB)
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continue;
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Register OtherSrcReg, OtherReg;
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unsigned OtherSrcSubReg, OtherSubReg;
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unsigned OtherSrcSubReg = 0, OtherSubReg = 0;
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if (!isMoveInstr(*TRI, &Copy, OtherSrcReg, OtherReg, OtherSrcSubReg,
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OtherSubReg))
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return false;
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@ -13830,7 +13830,7 @@ static SDValue lowerShuffleAsInsertPS(const SDLoc &DL, SDValue V1, SDValue V2,
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assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
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// Attempt to match the insertps pattern.
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unsigned InsertPSMask;
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unsigned InsertPSMask = 0;
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if (!matchShuffleAsInsertPS(V1, V2, InsertPSMask, Zeroable, Mask, DAG))
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return SDValue();
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