forked from OSchip/llvm-project
AMDGPU: More mad_64_32 test cases for multiple uses
Also use gfx90a for the gfx9 test, whose code gen should be affected by faster multiply-add instructions.
This commit is contained in:
Nicolai Hähnle
parent
20c873c12f
commit
b39d34de5e
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@ -1,7 +1,7 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefixes=CI %s
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; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=SI %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9 %s
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; RUN: llc -march=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9 %s
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define i64 @mad_i64_i32_sextops(i32 %arg0, i32 %arg1, i64 %arg2) #0 {
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; CI-LABEL: mad_i64_i32_sextops:
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@ -179,24 +179,26 @@ define i128 @mad_i64_i32_sextops_i32_i128(i32 %arg0, i32 %arg1, i128 %arg2) #0 {
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v0, v1, 0
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; GFX9-NEXT: v_ashrrev_i32_e32 v13, 31, v0
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; GFX9-NEXT: v_mov_b32_e32 v8, 0
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; GFX9-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v13, v1, v[7:8]
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; GFX9-NEXT: v_mov_b32_e32 v9, 0
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; GFX9-NEXT: v_mov_b32_e32 v8, v7
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; GFX9-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v13, v1, v[8:9]
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; GFX9-NEXT: v_ashrrev_i32_e32 v14, 31, v1
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; GFX9-NEXT: v_mad_i64_i32 v[11:12], s[4:5], v1, v13, 0
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; GFX9-NEXT: v_mov_b32_e32 v7, v10
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; GFX9-NEXT: v_mov_b32_e32 v10, v8
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; GFX9-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v0, v14, v[9:10]
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; GFX9-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v14, v0, v[11:12]
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; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v7, v9
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; GFX9-NEXT: v_addc_co_u32_e64 v10, s[4:5], 0, 0, vcc
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; GFX9-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v13, v14, v[9:10]
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; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v9, v0
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; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v10, v1, vcc
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; GFX9-NEXT: v_mov_b32_e32 v1, v8
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; GFX9-NEXT: v_mov_b32_e32 v8, v11
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; GFX9-NEXT: v_mov_b32_e32 v11, v9
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; GFX9-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v0, v14, v[10:11]
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; GFX9-NEXT: v_mov_b32_e32 v12, v11
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; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v8, v12
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; GFX9-NEXT: v_addc_co_u32_e64 v9, s[4:5], 0, 0, vcc
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; GFX9-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v13, v14, v[8:9]
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; GFX9-NEXT: v_mad_i64_i32 v[12:13], s[4:5], v1, v13, 0
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; GFX9-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v14, v0, v[12:13]
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; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v0
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; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v9, v1, vcc
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; GFX9-NEXT: v_mov_b32_e32 v1, v10
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; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v6, v2
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; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
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; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v7, v4, vcc
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; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v9, v5, vcc
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; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v5, vcc
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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%sext0 = sext i32 %arg0 to i128
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%sext1 = sext i32 %arg1 to i128
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@ -265,8 +267,8 @@ define i63 @mad_i64_i32_sextops_i31_i63(i31 %arg0, i31 %arg1, i63 %arg2) #0 {
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
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; GFX9-NEXT: v_bfe_i32 v1, v1, 0, 31
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; GFX9-NEXT: v_ashrrev_i64 v[2:3], 1, v[2:3]
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; GFX9-NEXT: v_bfe_i32 v1, v1, 0, 31
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; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 31
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; GFX9-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v0, v1, v[2:3]
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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@ -526,12 +528,11 @@ define amdgpu_kernel void @mad_i64_i32_uniform(i64 addrspace(1)* %out, i32 %arg0
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; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
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; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34
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; GFX9-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x24
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: v_mov_b32_e32 v2, s3
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; GFX9-NEXT: v_mov_b32_e32 v0, s4
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; GFX9-NEXT: v_mov_b32_e32 v1, s5
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; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s2, v2, v[0:1]
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; GFX9-NEXT: v_mov_b32_e32 v2, 0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: v_mov_b32_e32 v3, s3
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; GFX9-NEXT: v_pk_mov_b32 v[0:1], s[4:5], s[4:5] op_sel:[0,1]
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; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s2, v3, v[0:1]
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; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7]
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; GFX9-NEXT: s_endpgm
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%ext0 = zext i32 %arg0 to i64
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@ -542,8 +543,8 @@ define amdgpu_kernel void @mad_i64_i32_uniform(i64 addrspace(1)* %out, i32 %arg0
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ret void
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}
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define i64 @mad_i64_i32_multiple(i32 %arg0, i32 %arg1, i64 %arg2, i64 %arg3) #0 {
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; CI-LABEL: mad_i64_i32_multiple:
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define i64 @mad_i64_i32_twice(i32 %arg0, i32 %arg1, i64 %arg2, i64 %arg3) #0 {
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; CI-LABEL: mad_i64_i32_twice:
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; CI: ; %bb.0:
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; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CI-NEXT: v_mad_i64_i32 v[2:3], s[4:5], v0, v1, v[2:3]
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@ -552,7 +553,7 @@ define i64 @mad_i64_i32_multiple(i32 %arg0, i32 %arg1, i64 %arg2, i64 %arg3) #0
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; CI-NEXT: v_xor_b32_e32 v0, v2, v0
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; CI-NEXT: s_setpc_b64 s[30:31]
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;
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; SI-LABEL: mad_i64_i32_multiple:
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; SI-LABEL: mad_i64_i32_twice:
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; SI: ; %bb.0:
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; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SI-NEXT: v_mul_lo_u32 v6, v0, v1
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@ -565,7 +566,7 @@ define i64 @mad_i64_i32_multiple(i32 %arg0, i32 %arg1, i64 %arg2, i64 %arg3) #0
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; SI-NEXT: v_xor_b32_e32 v0, v2, v3
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; SI-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX9-LABEL: mad_i64_i32_multiple:
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; GFX9-LABEL: mad_i64_i32_twice:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_mad_i64_i32 v[2:3], s[4:5], v0, v1, v[2:3]
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@ -582,5 +583,94 @@ define i64 @mad_i64_i32_multiple(i32 %arg0, i32 %arg1, i64 %arg2, i64 %arg3) #0
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ret i64 %out
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}
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define i64 @mad_i64_i32_thrice(i32 %arg0, i32 %arg1, i64 %arg2, i64 %arg3, i64 %arg4) #0 {
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; CI-LABEL: mad_i64_i32_thrice:
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; CI: ; %bb.0:
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; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CI-NEXT: v_mad_i64_i32 v[2:3], s[4:5], v0, v1, v[2:3]
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; CI-NEXT: v_mad_i64_i32 v[4:5], s[4:5], v0, v1, v[4:5]
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; CI-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v0, v1, v[6:7]
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; CI-NEXT: v_xor_b32_e32 v3, v3, v5
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; CI-NEXT: v_xor_b32_e32 v2, v2, v4
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; CI-NEXT: v_xor_b32_e32 v1, v3, v1
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; CI-NEXT: v_xor_b32_e32 v0, v2, v0
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; CI-NEXT: s_setpc_b64 s[30:31]
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;
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; SI-LABEL: mad_i64_i32_thrice:
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; SI: ; %bb.0:
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; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SI-NEXT: v_mul_lo_u32 v8, v0, v1
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; SI-NEXT: v_mul_hi_i32 v0, v0, v1
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; SI-NEXT: v_add_i32_e32 v1, vcc, v8, v2
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; SI-NEXT: v_addc_u32_e32 v2, vcc, v0, v3, vcc
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; SI-NEXT: v_add_i32_e32 v3, vcc, v8, v4
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; SI-NEXT: v_addc_u32_e32 v4, vcc, v0, v5, vcc
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; SI-NEXT: v_add_i32_e32 v5, vcc, v8, v6
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; SI-NEXT: v_addc_u32_e32 v0, vcc, v0, v7, vcc
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; SI-NEXT: v_xor_b32_e32 v2, v2, v4
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; SI-NEXT: v_xor_b32_e32 v3, v1, v3
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; SI-NEXT: v_xor_b32_e32 v1, v2, v0
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; SI-NEXT: v_xor_b32_e32 v0, v3, v5
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; SI-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX9-LABEL: mad_i64_i32_thrice:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_mad_i64_i32 v[2:3], s[4:5], v0, v1, v[2:3]
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; GFX9-NEXT: v_mad_i64_i32 v[4:5], s[4:5], v0, v1, v[4:5]
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; GFX9-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v0, v1, v[6:7]
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; GFX9-NEXT: v_xor_b32_e32 v3, v3, v5
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; GFX9-NEXT: v_xor_b32_e32 v2, v2, v4
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; GFX9-NEXT: v_xor_b32_e32 v1, v3, v1
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; GFX9-NEXT: v_xor_b32_e32 v0, v2, v0
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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%sext0 = sext i32 %arg0 to i64
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%sext1 = sext i32 %arg1 to i64
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%mul = mul i64 %sext0, %sext1
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%mad1 = add i64 %mul, %arg2
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%mad2 = add i64 %mul, %arg3
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%mad3 = add i64 %mul, %arg4
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%out.p = xor i64 %mad1, %mad2
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%out = xor i64 %out.p, %mad3
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ret i64 %out
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}
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define i64 @mad_i64_i32_secondary_use(i32 %arg0, i32 %arg1, i64 %arg2) #0 {
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; CI-LABEL: mad_i64_i32_secondary_use:
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; CI: ; %bb.0:
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; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CI-NEXT: v_mad_i64_i32 v[4:5], s[4:5], v0, v1, 0
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; CI-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v0, v1, v[2:3]
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; CI-NEXT: v_xor_b32_e32 v1, v1, v5
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; CI-NEXT: v_xor_b32_e32 v0, v0, v4
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; CI-NEXT: s_setpc_b64 s[30:31]
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;
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; SI-LABEL: mad_i64_i32_secondary_use:
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; SI: ; %bb.0:
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; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SI-NEXT: v_mul_lo_u32 v4, v0, v1
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; SI-NEXT: v_mul_hi_i32 v0, v0, v1
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; SI-NEXT: v_add_i32_e32 v2, vcc, v4, v2
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; SI-NEXT: v_addc_u32_e32 v1, vcc, v0, v3, vcc
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; SI-NEXT: v_xor_b32_e32 v1, v1, v0
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; SI-NEXT: v_xor_b32_e32 v0, v2, v4
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; SI-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX9-LABEL: mad_i64_i32_secondary_use:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_mad_i64_i32 v[4:5], s[4:5], v0, v1, 0
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; GFX9-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v0, v1, v[2:3]
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; GFX9-NEXT: v_xor_b32_e32 v1, v1, v5
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; GFX9-NEXT: v_xor_b32_e32 v0, v0, v4
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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%sext0 = sext i32 %arg0 to i64
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%sext1 = sext i32 %arg1 to i64
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%mul = mul i64 %sext0, %sext1
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%mad = add i64 %mul, %arg2
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%out = xor i64 %mad, %mul
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ret i64 %out
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone speculatable }
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